MC68HC908QL4 Datasheet, PDF (121/226 Pages) Motorola, Inc – Microcontrollers

IRST
RST
BUSCLKX4
ADDRESS
BUS
Reset and System Initialization
RST PULLED LOW BY MCU
32 CYCLES
32 CYCLES
Figure 13-4. Internal Reset Timing
VECTOR HIGH
ILLEGAL ADDRESS RST
ILLEGAL OPCODE RST
COPRST
POR
LVI
INTERNAL RESET
Figure 13-5. Sources of Internal Reset
Table 13-2. Reset Recovery Timing
Reset Recovery Type
POR/LVI
All others
Actual Number of Cycles
4163 (4096 + 64 + 3)
67 (64 + 3)
13.4.2.1 Power-On Reset
When power is first applied to the MCU, the power-on reset module (POR) generates a pulse to indicate
that power on has occurred. The SIM counter counts out 4096 BUSCLKX4 cycles. Sixty-four BUSCLKX4
cycles later, the CPU and memories are released from reset to allow the reset vector sequence to occur.
At power on, the following events occur:
• A POR pulse is generated.
• The internal reset signal is asserted.
• The SIM enables the oscillator to drive BUSCLKX4.
• Internal clocks to the CPU and modules are held inactive for 4096 BUSCLKX4 cycles to allow
stabilization of the oscillator.
• The POR bit of the SIM reset status register (SRSR) is set.
See Figure 13-6.
MC68HC908QL4 Data Sheet, Rev. 7
Freescale Semiconductor
121