MC68HC908QL4 Datasheet, PDF (175/226 Pages) Motorola, Inc – Microcontrollers

TCLK
(IF AVAILABLE)
INTERNAL
BUS CLOCK
TCLK
PRESCALER
TSTOP
TRST
16-BIT COUNTER
TCNTH:TCNTL
16-BIT COMPARATOR
TMODH:TMODL
CHANNEL 0
16-BIT COMPARATOR
TCH0H:TCH0L
16-BIT LATCH
CHANNEL 1
16-BIT COMPARATOR
TCH1H:TCH1L
16-BIT LATCH
PRESCALER SELECT
PS2
PS1
PS0
ELS0B ELS0A
CH0F
MS0A
MS0B
ELS1B ELS1A
MS1A
CH1F
Functional Description
TOF
INTERRUPT
TOIE
LOGIC
TOV0
CH0MAX
CH0IE
TOV1
CH1MAX
CH1IE
PORT
LOGIC
TCH0
INTERRUPT
LOGIC
PORT
LOGIC
TCH1
INTERRUPT
LOGIC
Figure 15-2. TIM Block Diagram
15.3.3.1 Unbuffered Output Compare
Any output compare channel can generate unbuffered output compare pulses as described in 15.3.3
Output Compare. The pulses are unbuffered because changing the output compare value requires writing
the new value over the old value currently in the TIM channel registers.
An unsynchronized write to the TIM channel registers to change an output compare value could cause
incorrect operation for up to two counter overflow periods. For example, writing a new value before the
counter reaches the old value but after the counter reaches the new value prevents any compare during
that counter overflow period. Also, using a TIM overflow interrupt routine to write a new, smaller output
compare value may cause the compare to be missed. The TIM may pass the new value before it is written.
Use the following methods to synchronize unbuffered changes in the output compare value on channel x:
• When changing to a smaller value, enable channel x output compare interrupts and write the new
value in the output compare interrupt routine. The output compare interrupt occurs at the end of
the current output compare pulse. The interrupt routine has until the end of the counter overflow
period to write the new value.
MC68HC908QL4 Data Sheet, Rev. 7
Freescale Semiconductor
175