MC68HC908QL4 Datasheet, PDF (164/226 Pages) Motorola, Inc – Microcontrollers

Slave LIN Interface Controller (SLIC) Module
delay values (cutoff values) are shown in the frequency and time domains. Note that Table 14-7 shows
the filter performance under ideal conditions.
When switching between a low-speed (< 4800 bps) to a high-speed (> 40000 bps) LIN message, the
master node must allow a minimum idle time of eight bit times (of the slowest bit rate) between the
messages. This prevents a valid message at another frequency from being detected as an invalid
message.
Table 14-6. Maximum LIN Bit Rates for High-Speed Operation Due to Digital Receive Filter
SLIC
Clock
(MHz)
8
6.4
4.8
4
3.2
2.4
2
Maximum LIN
Bit Rate for ±1.5%
SLIC Accuracy
(for Master-Slave
Communication
(Bits / Second)
DIGITAL RX FILTER
NOT CONSIDERED
120,000
96,000
72,000
60,000
48,000
36,000
30,000
Maximum LIN
Bit Rate with
Digital RX Filter
Set to ÷4
(Bits / Second)
Maximum LIN
Bit Rate with
Digital RX Filter
Set to ÷3
(Bits / Second)
THESE PRESCALERS
NOT RECOMMENDED FOR
HIGH-SPEED LIN OPERATION
120,000⁽¹⁾
100,000
120,000⁽¹⁾
120,000⁽¹⁾
75,000
100,000
62,500
83,333
50,000
66,667
37,500
50,000
31,250
41,667
Maximum LIN
Bit Rate with
Digital RX Filter
Set to ÷2
(Bits / Second)
120,000⁽¹⁾
120,000⁽¹⁾
120,000⁽¹⁾
120,000⁽¹⁾
100,000
75,000
62,500
Maximum LIN
Bit Rate with
Digital RX Filter
Set to ÷1
(Bits / Second)
120,000⁽¹⁾
120,000⁽¹⁾
120,000⁽¹⁾
120,000⁽¹⁾
120,000⁽¹⁾
120,000⁽¹⁾
120,000⁽¹⁾
1. Bit rates over 120,000 bits per second are not recommended for LIN communications, as physical layer delay between the
TX and RX pins can cause the stop bit of a byte to be mis-sampled as the last data bit. This could result in a byte framing
error.
SLIC
Clock
(MHz)
8
6.4
4.8
4
3.2
2.4
2
Table 14-7. Digital Receive Filter Absolute Cutoff (Ideal Conditions)
Digital RX Filter
Set to ÷4
Max.
Bit Rate
(Bits /
Sec)
Min Pulse
Width
Allowed
(μs)
125,000
8.0
100,000
10.0
75,000
13.3
62,500
16.0
50,000
20.0
37,500
26.7
31,250
32.0
Digital RX Filter
Set to ÷3
Max.
Bit Rate
(Bits /
Sec)
Min Pulse
Width
Allowed
(μs)
166,667
6.0
133,333
7.5
100,000
10.0
83,333
12.0
66,667
15.0
50,000
20.0
41,667
24.0
Digital RX Filter
Set to ÷2
Max.
Bit Rate
(Bits /
Sec)
Min Pulse
Width
Allowed
(μs)
250,000
4.0
200,000
5.0
150,000
6.7
125,000
8.0
100,000
10.0
75,000
13.3
62,500
16.0
Digital RX Filter
Set to ÷1
Max.
Bit Rate
(Bits /
Sec)
Min Pulse
Width
Allowed
(μs)
500,000
2.0
400,000
2.5
300,000
3.3
250,000
4.0
200,000
5.0
150,000
6.7
125,000
8.0
MC68HC908QL4 Data Sheet, Rev. 7
164
Freescale Semiconductor