MC68HC908QL4 Datasheet, PDF (143/226 Pages) Motorola, Inc – Microcontrollers

Registers
high-speed downloads for reprogramming of FLASH memory or diagnostics in a test environment where
radiated emissions requirements are not as stringent. In these situations, the user may choose to run
faster than the 20 kbps limit which is imposed by the LIN specification for EMC reasons. Details of how
to calculate maximum bit rates and operate the SLIC above 20 kbps are detailed in 14.9.14 High-Speed
LIN Operation. Refer to 14.9.6 SLIC Module Initialization Procedure for more information on when to set
up this register.
14.8.5 SLIC Bit Time Registers
NOTE
In this subsection, the SLIC bit time registers are collectively referred to as
SLCBT.
In LIN operating mode (BTM = 0), the SLCBT is updated by the SLIC upon reception of a LIN break-synch
combination and provides the number of SLIC clock counts that equal one LIN bit time to the user
software. This value can be used by the software to calculate the clock drift in the oscillator as an offset
to a known count value (based on nominal oscillator frequency and LIN bus speed). The user software
can then trim the oscillator to compensate for clock drift. Refer to 14.9.16 Oscillator Trimming with SLIC
for more information on this procedure. The user cannot read the bit time value from SLCBTH and
SLCBTL any time after the identifier byte is received until the beginning of the next LIN message frame
on the bus. The beginning of this message frame activity will be indicated by SLCACT.
When in byte transfer mode (BTM = 1), the SLCBT must be written by the user to set the length of one
bit at the desired bit rate in SLIC clock counts. The user software must initialize this number prior to
sending or receiving data, based on the input clock selection, prescaler stage choice, and desired bit rate.
This setting is similar to choosing an input capture or output compare value for a timer. The closest even
value must be chosen for this value, as BT0 will be forced to 0 by the SLIC module and any odd value will
always be reduced to the next lowest even integer value. For example, a write of value 51 (0x33) will be
forced to value of 50 and read back as 0x32. A write to both registers is required to update the bit time
value.
NOTE
The SLIC bit time will not be updated until a write of the SLCBTL has
occurred.
Bit 7
Read: 0
Write:
Reset: 0
6
5
0
0
0
0
= Unimplemented
4
3
2
1
Bit 0
BT12
BT11
BT10
BT9
BT8
0
0
0
0
0
Figure 14-8. SLIC Bit Time Register High (SLCBTH)
Bit 7
6
5
4
3
2
1
Bit 0
Read:
0
BT7
BT6
BT5
BT4
BT3
BT2
BT1
Write:
Reset: 0
0
0
0
0
0
0
0
= Unimplemented
Figure 14-9. SLIC Bit Time Register Low (SLCBTL)
MC68HC908QL4 Data Sheet, Rev. 7
Freescale Semiconductor
143