MC68HC908QL4 Datasheet, PDF (125/226 Pages) Motorola, Inc – Microcontrollers

Exception Control
Interrupts are latched, and arbitration is performed in the SIM at the start of interrupt processing. The
arbitration result is a constant that the CPU uses to determine which vector to fetch. Once an interrupt is
latched by the SIM, no other interrupt can take precedence, regardless of priority, until the latched
interrupt is serviced (or the I bit is cleared).
At the beginning of an interrupt, the CPU saves the CPU register contents on the stack and sets the
interrupt mask (I bit) to prevent additional interrupts. At the end of an interrupt, the RTI instruction recovers
the CPU register contents from the stack so that normal processing can resume. Figure 13-8 shows
interrupt entry timing. Figure 13-9 shows interrupt recovery timing.
MODULE
INTERRUPT
I BIT
ADDRESS BUS
DATA BUS
R/W
DUMMY
SP
SP – 1 SP – 2 SP – 3 SP – 4 VECT H VECT L START ADDR
DUMMY PC – 1[7:0] PC – 1[15:8] X
A
CCR V DATA H V DATA L OPCODE
Figure 13-8. Interrupt Entry
MODULE
INTERRUPT
I BIT
ADDRESS BUS
DATA BUS
R/W
SP – 4 SP – 3 SP – 2 SP – 1
SP
PC
PC + 1
CCR
A
X
PC – 1[7:0] PC – 1[15:8] OPCODE OPERAND
Figure 13-9. Interrupt Recovery
MC68HC908QL4 Data Sheet, Rev. 7
Freescale Semiconductor
125