MC68HC908QL4 Datasheet, PDF (144/226 Pages) Motorola, Inc – Microcontrollers

Slave LIN Interface Controller (SLIC) Module
BT — Bit Time Value
BT displays the number of SLIC clocks that equals one bit time in LIN mode (BTM = 0). For details of
the use of the SLCBT registers in LIN mode for trimming of the internal oscillator, refer to 14.9.16
Oscillator Trimming with SLIC.
BT sets the number of SLIC clocks that equals one bit time in byte transfer mode (BTM = 1). For details
of the use of the SLCBT registers in BTM mode, refer to 14.9.15 Byte Transfer Mode Operation.
NOTE
Do not write to unimplemented bits as unexpected operation may occur.
14.8.6 SLIC State Vector Register
SLIC state vector register (SLCSV) is provided to substantially decrease the CPU overhead associated
with servicing interrupts while under operation of a LIN protocol. It provides an index offset that is directly
related to the LIN module’s current state, which can be used with a user supplied jump table to rapidly
enter an interrupt service routine. This eliminates the need for the user to maintain a duplicate state
machine in software.
Bit 7
6
5
4
3
2
1
Bit 0
Read: 0
0
I3
I2
I1
I0
0
0
Write:
Reset: 0
0
0
0
0
0
0
0
= Unimplemented
Figure 14-10. SLIC State Vector Register (SLCSV)
READ: any time
WRITE: ignored
I[3:0] — Interrupt State Vector (Bits 5–2)
These bits indicate the source of the interrupt request that is currently pending.
14.8.6.1 LIN Mode Operation
Table 14-2 shows the possible values for the possible sources for a SLIC interrupt while in LIN mode
operation (BTM = 0).
Table 14-2. Interrupt Sources Summary (BTM = 0)
SLCSV I3 I2 I1 I0
$00
0000
$04
0001
$08
0010
$0C
0011
$10
0100
$14
0101
$18
0110
Interrupt Source
No Interrupts Pending
No-Bus-Activity
TX Message Buffer Empty
Checksum Transmitted
TX Message Buffer Empty
RX Message Buffer Full
Checksum OK
RX Data Buffer Full
No Errors
Bit-Error
Priority
0 (Lowest)
1
2
3
4
5
6
MC68HC908QL4 Data Sheet, Rev. 7
144
Freescale Semiconductor