MC68HC908QL4 Datasheet, PDF (163/226 Pages) Motorola, Inc – Microcontrollers

Initialization/Application Information
14.9.14 High-Speed LIN Operation
High-speed LIN operation does not necessarily require any reconfiguration of the SLIC module,
depending upon what maximum LIN bit rate is desired. Several factors affect the performance of the SLIC
module at LIN speeds higher than 20 kbps, all of which are functions of the speed of the SLIC clock and
the prescaler of the digital filter. The tightest constraint comes from the need to maintain ±1.5% accuracy
with the master node timing. This requires that the SLIC module be able to sample the incoming data
stream accurately enough to guarantee that accuracy. Table 14-5 shows the maximum LIN bit rates
allowable to maintain this accuracy.
Table 14-5. Maximum LIN Bit Rates for High-Speed Operation
SLIC Clock (MHz)
8
6.4
4.8
4
3.2
2.4
2
Maximum LIN Bit Rate
for ±1% SLIC Accuracy
(Bits / Second)
80,000
64,000
48,000
40,000
32,000
24,000
20,000
Maximum LIN Bit Rate
for ±1.5% SLIC Accuracy
(Bits / Second)
120,000
96,000
72,000
60,000
48,000
36,000
30,000
The above numbers assume a perfect input waveforms into the SLCRX pin, where 1 and 0 bits are of
equal length and are exactly the correct length for the appropriate speed. Factors such as physical layer
wave shaping and ground shift can affect the symmetry of these waveforms, causing bits to appear
shortened or lengthened as seen by the SLIC module. The user must take these factors into account and
base the maximum speed upon the shortest possible bit time that the SLIC module may observe, factoring
in all physical layer effects. On some LIN physical layer devices it is possible to turn off wave shaping
circuitry for high-speed operation, removing this portion of the physical layer error.
The digital receive filter can also affect high speed operation if it is set too low and begins to filter out valid
message traffic. Under ideal conditions, this will not happen, as the digital filter maximum speeds
allowable are higher than the speeds allowed for ±1.5% accuracy. If the digital receive filter prescaler is
set to divide- by-4; however, the filter delay is very close to the ±1.5% accuracy maximum bit time.
For example, with a SLIC clock of 4 MHz, the SLIC module is capable of maintaining ±1.5% accuracy up
to 60,000 bps. If the digital receive filter prescaler is set to divide-by-4, this means that the filter will only
pass message traffic which is 62,500 bps or slower under ideal circumstances. This is only a difference
of 2,500 bps (4.17% of the nominal valid message traffic speed). In this case, the user must ensure that
with all errors accounted for, no bit will appear shorter than 16 μs
(1 bit at 62,500 bps) or the filter will block that bit. This is far too narrow a margin for safe design practices.
The better solution would be to reduce the filter prescaler, increasing the gap between the filter cut-off
point and the nominal speed of valid message traffic. Changing the prescaler to divide by 2 in this example
gives a filter cut-off of 125,000 bps, which is 60,000 bps faster than the nominal speed of the LIN bus and
much less likely to interfere with valid message traffic.
To ensure that all valid messages pass the filter stage in high-speed operation, it is best to ensure that
the filter cut-off point is at least 2 times the nominal speed of the fastest message traffic to appear on the
bus. Refer to Table 14-6 for a more complete list of the digital receive filter delays as they relate to the
maximum LIN bus frequency. Table 14-7 repeats much of the data found in Table 14-6; however, the filter
MC68HC908QL4 Data Sheet, Rev. 7
Freescale Semiconductor
163