MC68HC908QL4 Datasheet, PDF (171/226 Pages) Motorola, Inc – Microcontrollers

Initialization/Application Information
signal to become a logic level 0. Furthermore, the counter is prevented from underflowing and can only
be incremented from this state.
The data latch will retain its value until the counter next reaches the opposite end point, signifying a
definite transition of the SLCRX signal.
14.9.17.2 Digital Filter Performance
The performance of the digital filter is best described in the time domain rather than the frequency domain.
If the signal on the SLCRX signal transitions, then there will be a delay before that transition appears at
the filtered Rx data output signal. This delay will be between 15 and 16 clock periods, depending on where
the transition occurs with respect to the sampling points. This ‘filter delay’ is not an issue for SLIC
operation, as there is no need for message arbitration.
The effect of random noise on the SLCRX signal depends on the characteristics of the noise itself. Narrow
noise pulses on the SLCRX signal will be completely ignored if they are shorter than the filter delay. This
provides a degree of low-pass filtering. Figure 14-23 shows the configuration of the digital receive filter
and the consequential effect on the filter delay. This filter delay value indicates that for a particular setup,
only pulses of which are greater than the filter delay will pass the filter.
For example, if the frequency of the SLIC clock (f_SLIC) is 3.2 MHz, then the period (t_SLIC) is of the SLIC
clock is 313 ns. With the default receive filter prescaler setting of division by 3, the resulting maximum
filter delay in the absence of noise will be 15.00 μs. By simply changing the prescaler of the receive filter,
the user can then select alternatively 5 μs, 10 μs, or 20 μs as a minimum filter delay according to the
systems requirements.
If noise occurs during a symbol transition, the detection of that transition may be delayed by an amount
equal to the length of the noise burst. This is just a reflection of the uncertainty of where the transition is
truly occurring within the noise.
NOTE
The user must always account for the worst case bit timing of their LIN bus
when configuring the digital receive filter, especially if running at faster
speeds. Ground offset and other physical layer conditions can cause
shortening of bits as seen at the digital receive pin, for example. If these
shortened bit lengths are less than the filter delay, the bits will be
interpreted by the filter as noise and will be blocked, even though the
nominal bit timing might be greater than the filter delay.
MC68HC908QL4 Data Sheet, Rev. 7
Freescale Semiconductor
171