MC68HC908QL4 Datasheet, PDF (113/226 Pages) Motorola, Inc – Microcontrollers

READ DDRA
WRITE DDRA
WRITE PTA
RESET
DDRAx
PTAx
PTAPUEx
KBIPx
Port A
R_PULL
PTAx
READ PTA
Figure 12-3. Port A I/O Circuit
NOTE
Figure 12-3 does not apply to PTA2
When DDRAx is a 1, reading PTA reads the PTAx data latch. When DDRAx is a 0, reading PTA reads
the logic level on the PTAx pin. The data latch can always be written, regardless of the state of its data
direction bit.
12.3.3 Port A Input Pullup/Down Enable Register
The port A input pullup/down enable register (PTAPUE) contains a software configurable pullup/down
device for each of the port A pins. Each bit is individually configurable and requires the corresponding
data direction register, DDRAx, to be configured as input. Each pullup/down device is automatically and
dynamically disabled when its corresponding DDRAx bit is configured as output. The pull device polarity
is defined by the KBIPR register, see 9.8.3 Keyboard Interrupt Polarity Register (KBIPR).
Bit 7
Read:
OSC2EN
Write:
Reset: 0
6
5
4
3
2
1
Bit 0
PTAPUE5 PTAPUE4 PTAPUE3 PTAPUE2 PTAPUE1 PTAPUE0
0
0
0
0
0
0
0
= Unimplemented
Figure 12-4. Port A Input Pullup/Down Enable Register (PTAPUE)
OSC2EN — Enable PTA4 on OSC2 Pin
This read/write bit configures the OSC2 pin function when internal oscillator or RC oscillator option is
selected. This bit has no effect for the XTAL or external oscillator options.
1 = OSC2 pin outputs the internal or RC oscillator clock (BUSCLKX4)
0 = OSC2 pin configured for PTA4 I/O, having all the interrupt and pullup/down functions
MC68HC908QL4 Data Sheet, Rev. 7
Freescale Semiconductor
113