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MC68HC908QL4 Datasheet, PDF (180/226 Pages) Motorola, Inc – Microcontrollers
Timer Interface Module (TIM)
15.7.1 TIM Channel I/O Pins (TCH1:TCH0)
Each channel I/O pin is programmable independently as an input capture pin or an output compare pin.
TCH0 can be configured as buffered output compare or buffered PWM pin.
15.7.2 TIM Clock Pin (TCLK)
TCLK is an external clock input that can be the clock source for the counter instead of the prescaled
internal bus clock. Select the TCLK input by writing 1s to the three prescaler select bits, PS[2:0]. The
minimum TCLK pulse width is specified in the Timer Interface Module Characteristics table in the
Electricals section. The maximum TCLK frequency is the least of 4 MHz or bus frequency ÷ 2.
15.8 Registers
The following registers control and monitor operation of the TIM:
• TIM status and control register (TSC)
• TIM control registers (TCNTH:TCNTL)
• TIM counter modulo registers (TMODH:TMODL)
• TIM channel status and control registers (TSC0 and TSC1)
• TIM channel registers (TCH0H:TCH0L and TCH1H:TCH1L)
15.8.1 TIM Status and Control Register
The TIM status and control register (TSC) does the following:
• Enables TIM overflow interrupts
• Flags TIM overflows
• Stops the counter
• Resets the counter
• Prescales the counter clock
Bit 7
6
5
4
3
Read: TOF
0
0
TOIE TSTOP
Write: 0
TRST
Reset: 0
0
1
0
0
= Unimplemented
2
1
Bit 0
PS2
PS1
PS0
0
0
0
Figure 15-4. TIM Status and Control Register (TSC)
TOF — TIM Overflow Flag Bit
This read/write flag is set when the counter reaches the modulo value programmed in the TIM counter
modulo registers. Clear TOF by reading the TSC register when TOF is set and then writing a 0 to TOF.
If another TIM overflow occurs before the clearing sequence is complete, then writing 0 to TOF has no
effect. Therefore, a TOF interrupt request cannot be lost due to inadvertent clearing of TOF. Writing a
1 to TOF has no effect.
1 = Counter has reached modulo value
0 = Counter has not reached modulo value
MC68HC908QL4 Data Sheet, Rev. 7
180
Freescale Semiconductor