MC68HC908QL4 Datasheet, PDF (112/226 Pages) Motorola, Inc – Microcontrollers

Input/Output Ports (PORTS)
12.3.1 Port A Data Register
The port A data register (PTA) contains a data latch for each of the six port A pins.
Bit 7
6
5
4
3
2
1
Bit 0
Read:
R
Write:
AWUL
PTA5
PTA4
PTA3
PTA2
PTA1
PTA0
Reset:
Unaffected by reset
R
= Reserved
= Unimplemented
Figure 12-1. Port A Data Register (PTA)
PTA[5:0] — Port A Data Bits
These read/write bits are software programmable. Data direction of each port A pin is under the control
of the corresponding bit in data direction register A. Reset has no effect on port A data.
AWUL — Auto Wakeup Latch Data Bit
This is a read-only bit which has the value of the auto wakeup interrupt request latch. The wakeup
request signal is generated internally (see Chapter 4 Auto Wakeup Module (AWU)). There is no PTA6
port nor any of the associated bits such as PTA6 data register, pullup/down enable or direction.
12.3.2 Data Direction Register A
Data direction register A (DDRA) determines whether each port A pin is an input or an output. Writing a
1 to a DDRA bit enables the output buffer for the corresponding port A pin; a 0 disables the output buffer.
Read:
Write:
Reset:
Bit 7
6
5
4
3
2
1
0
R
R
DDRA5 DDRA4 DDRA3
DDRA1
0
0
0
0
0
0
0
R
= Reserved
= Unimplemented
Figure 12-2. Data Direction Register A (DDRA)
Bit 0
DDRA0
0
DDRA[5:0] — Data Direction Register A Bits
These read/write bits control port A data direction. Reset clears DDRA[5:0], configuring all port A pins
as inputs.
1 = Corresponding port A pin configured as output
0 = Corresponding port A pin configured as input
NOTE
Avoid glitches on port A pins by writing to the port A data register before
changing data direction register A bits from 0 to 1.
Figure 12-3 shows the port A I/O logic.
MC68HC908QL4 Data Sheet, Rev. 7
112
Freescale Semiconductor