MC68HC908GR8A_07 Datasheet, PDF (65/260 Pages) Freescale Semiconductor, Inc – Microcontrollers

4.5 CGM Registers
These registers control and monitor operation of the CGM:
• PLL control register (PCTL)
(See 4.5.1 PLL Control Register.)
• PLL bandwidth control register (PBWC)
(See 4.5.2 PLL Bandwidth Control Register.)
• PLL multiplier select register high (PMSH)
(See 4.5.3 PLL Multiplier Select Register High.)
• PLL multiplier select register low (PMSL)
(See 4.5.4 PLL Multiplier Select Register Low.)
• PLL VCO range select register (PMRS)
(See 4.5.5 PLL VCO Range Select Register.)
• PLL reference divider select register (PMDS)
(See 4.5.6 PLL Reference Divider Select Register.)
Figure 4-3 is a summary of the CGM registers.
CGM Registers
Addr.
Register Name
Bit 7
6
5
4
3
$0036
Read:
PLLF
PLL Control Register
(PCTL)
Write:
PLLIE
PLLON
BCS
Reset: 0
0
1
0
PRE1
0
Read:
LOCK
0
0
$0037
PLL Bandwidth Control
Register (PBWC)
Write:
AUTO
ACQ
Reset: 0
0
0
0
0
Read: 0
0
0
0
$0038
PLL Multiplier Select High
Register (PMSH)
Write:
MUL11
Reset: 0
0
0
0
0
$0039
Read:
PLL Multiplier Select Low
Register (PMSL)
Write:
Reset:
MUL7
0
MUL6
1
MUL5
0
MUL4
0
MUL3
0
$003A
Read:
PLL VCO Select Range
Register (PMRS)
Write:
Reset:
VRS7
0
VRS6
1
VRS5
0
VRS4
0
VRS3
0
Read: 0
0
0
0
$003B
PLL Reference Divider
Select Register (PMDS)
Write:
RDS3
Reset: 0
0
0
0
0
= Unimplemented
R = Reserved
NOTES:
1. When AUTO = 0, PLLIE is forced clear and is read-only.
2. When AUTO = 0, PLLF and LOCK read as clear.
3. When AUTO = 1, ACQ is read-only.
4. When PLLON = 0 or VRS7:VRS0 = $0, BCS is forced clear and is read-only.
5. When PLLON = 1, the PLL programming register is read-only.
6. When BCS = 1, PLLON is forced set and is read-only.
Figure 4-3. CGM I/O Register Summary
2
PRE0
0
0
0
MUL10
0
MUL2
0
VRS2
0
RDS2
0
1
VPR1
0
0
0
MUL9
0
MUL1
0
VRS1
0
RDS1
0
Bit 0
VPR0
0
R
0
MUL8
0
MUL0
0
VRS0
0
RDS0
1
MC68HC908GR8A • MC68HC908GR4A Data Sheet, Rev. 5
Freescale Semiconductor
65