MC68HC908GR8A_07 Datasheet, PDF (127/260 Pages) Freescale Semiconductor, Inc – Microcontrollers

Port E
12.5.3 Port D Input Pullup Enable Register
The port D input pullup enable register (PTDPUE) contains a software configurable pullup device for each
of the seven port D pins. Each bit is individually configurable and requires that the data direction register,
DDRD, bit be configured as an input. Each pullup is automatically and dynamically disabled when a port
bit’s DDRD is configured for output mode.
Address: $000F
Bit 7
6
5
4
3
2
1
Bit 0
Read: 0
Write:
PTDPUE6 PTDPUE5 PTDPUE4 PTDPUE3 PTDPUE2 PTDPUE1 PTDPUE0
Reset: 0
0
0
0
0
0
0
0
Figure 12-16. Port D Input Pullup Enable Register (PTDPUE)
PTDPUE6–PTDPUE0 — Port D Input Pullup Enable Bits
These writable bits are software programmable to enable pullup devices on an input port bit.
1 = Corresponding port D pin configured to have internal pullup
0 = Corresponding port D pin has internal pullup disconnected
12.6 Port E
Port E is a 2-bit special-function port that shares two of its pins with the serial communications interface
(SCI) module.
12.6.1 Port E Data Register
The port E data register contains a data latch for each of the two port E pins.
Address: $0008
Bit 7
6
Read: 0
0
Write:
Reset:
Alternative
Function:
5
4
3
2
1
Bit 0
0
0
0
0
PTE1
PTE0
Unaffected by reset
RxD
TxD
= Unimplemented
Figure 12-17. Port E Data Register (PTE)
PTE1–PTE0 — Port E Data Bits
These read/write bits are software-programmable. Data direction of each port E pin is under the control
of the corresponding bit in data direction register E. Reset has no effect on port E data.
NOTE
Data direction register E (DDRE) does not affect the data direction of port
E pins that are being used by the ESCI module. However, the DDRE bits
always determine whether reading port E returns the states of the latches
or the states of the pins. See Table 12-6.
MC68HC908GR8A • MC68HC908GR4A Data Sheet, Rev. 5
Freescale Semiconductor
127