MC68HC908GR8A_07 Datasheet, PDF (119/260 Pages) Freescale Semiconductor, Inc – Microcontrollers

Port A
When bit DDRAx is a 1, reading address $0000 reads the PTAx data latch. When bit DDRAx is a 0,
reading address $0000 reads the voltage level on the pin. The data latch can always be written,
regardless of the state of its data direction bit. Table 12-2 summarizes the operation of the port A pins.
Table 12-2. Port A Pin Functions
PTAPUE
Bit
DDRA
Bit
PTA
Bit
I/O Pin
Mode
1
0
X⁽¹⁾
Input, V_DD(2)
0
0
X
Input, Hi-Z⁽⁴⁾
X
1
X
Output
1. X = Don’t care
2. I/O pin pulled up to V_DD by internal pullup device
3. Writing affects data register, but does not affect input.
4. Hi-Z = High impedance
Accesses to DDRA
Read/Write
DDRA3–DDRA0
DDRA3–DDRA0
DDRA3–DDRA0
Accesses to PTA
Read
Write
Pin
PTA3–PTA0⁽³⁾
Pin
PTA3–PTA0⁽³⁾
PTA3–PTA0
PTA3–PTA0
12.2.3 Port A Input Pullup Enable Register
The port A input pullup enable register (PTAPUE) contains a software configurable pullup device for each
of the four port A pins. Each bit is individually configurable and requires that the data direction register,
DDRA, bit be configured as an input. Each pullup is automatically and dynamically disabled when a port
bit’s DDRA is configured for output mode.
Address:
Read:
Write:
Reset:
$000D
Bit 7
0
0
6
5
0
0
0
0
= Unimplemented
4
3
2
1
Bit 0
0
PTAPUE3 PTAPUE2 PTAPUE1 PTAPUE0
0
0
0
0
0
Figure 12-5. Port A Input Pullup Enable Register (PTAPUE)
PTAPUE3–PTAPUE0 — Port A Input Pullup Enable Bits
These writeable bits are software programmable to enable pullup devices on an input port bit.
1 = Corresponding port A pin configured to have internal pullup
0 = Corresponding port A pin has internal pullup disconnected
MC68HC908GR8A • MC68HC908GR4A Data Sheet, Rev. 5
Freescale Semiconductor
119