MC68HC908GR8A_07 Datasheet, PDF (193/260 Pages) Freescale Semiconductor, Inc – Microcontrollers

I/O Registers
OVRF — Overflow Bit
This clearable, read-only flag is set if software does not read the byte in the receive data register before
the next full byte enters the shift register. In an overflow condition, the byte already in the receive data
register is unaffected, and the byte that shifted in last is lost. Clear the OVRF bit by reading the SPI
status and control register with OVRF set and then reading the receive data register. Reset clears the
OVRF bit.
1 = Overflow
0 = No overflow
MODF — Mode Fault Bit
This clearable, read-only flag is set in a slave SPI if the SS pin goes high during a transmission with
MODFEN set. In a master SPI, the MODF flag is set if the SS pin goes low at any time with the
MODFEN bit set. Clear MODF by reading the SPI status and control register (SPSCR) with MODF set
and then writing to the SPI control register (SPCR). Reset clears the MODF bit.
1 = SS pin at inappropriate logic level
0 = SS pin at appropriate logic level
SPTE — SPI Transmitter Empty Bit
This clearable, read-only flag is set each time the transmit data register transfers a byte into the shift
register. SPTE generates an SPTE CPU interrupt request if SPTIE in the SPI control register is set
also.
NOTE
Do not write to the SPI data register unless SPTE is high.
During an SPTE CPU interrupt, the CPU clears SPTE bit writing to the transmit data register. Reset
sets the SPTE bit.
1 = Transmit data register empty
0 = Transmit data register not empty
MODFEN — Mode Fault Enable Bit
This read/write bit, when set, allows the MODF flag to be set. If the MODF flag is set, clearing
MODFEN does not clear the MODF flag. If the SPI is enabled as a master and the MODFEN bit is 0,
then the SS pin is available as a general-purpose I/O.
If the MODFEN bit is 1, then the SS is not available as a general-purpose I/O. When the SPI is enabled
as a slave, the SS pin is not available as a general-purpose I/O regardless of the value of MODFEN.
See 15.11.4 SS (Slave Select).
If the MODFEN bit is 0, the level of the SS pin does not affect the operation of an enabled SPI
configured as a master. For an enabled SPI configured as a slave, having MODFEN low only prevents
the MODF flag from being set. It does not affect any other part of SPI operation. See 15.6.2 Mode Fault
Error.
SPR1 and SPR0 — SPI Baud Rate Select Bits
In master mode, these read/write bits select one of four baud rates as shown in Table 15-3. SPR1 and
SPR0 have no effect in slave mode. Reset clears SPR1 and SPR0.
Table 15-3. SPI Master Baud Rate Selection
SPR1 and SPR0
00
01
10
11
Baud Rate Divisor (BD)
2
8
32
128
MC68HC908GR8A • MC68HC908GR4A Data Sheet, Rev. 5
Freescale Semiconductor
193