MC68HC908GR8A_07 Datasheet, PDF (158/260 Pages) Freescale Semiconductor, Inc – Microcontrollers

System Integration Module (SIM)
The SIM is responsible for:
• Bus clock generation and control for CPU and peripherals:
– Stop/wait/reset/break entry and recovery
– Internal clock control
• Master reset control, including power-on reset (POR) and computer operating properly (COP)
timeout
• Interrupt arbitration
Table 14-1 shows the internal signal names used in this section.
Table 14-1. Signal Name Conventions
Signal Name
CGMXCLK
CGMVCLK
CGMOUT
IAB
IDB
PORRST
IRST
R/W
Description
Buffered version of OSC1 from clock generator module (CGM)
PLL output
PLL-based or OSC1-based clock output from CGM module
(Bus clock = CGMOUT divided by two)
Internal address bus
Internal data bus
Signal from the power-on reset module to the SIM
Internal reset signal
Read/write signal
Addr.
Register Name
Bit 7
6
5
4
3
2
1
Bit 0
SIM Break Status Register ^Read:
R
$FE00
(SBSR) Write:
R
R
R
R
SBSW
R
Note⁽¹⁾
R
See page 171. _{Reset: 0}
0
0
0
0
0
0
0
1. Writing a 0 clears SBSW.
SIM Reset Status Register ^{Read: POR}
PIN
COP
ILOP
ILAD MODRST LVI
0
$FE01
(SRSR) Write:
See page 172. _{POR: 1}
0
0
0
0
0
0
0
SIM Break Flag Control ^Read: _BCFE
R
R
R
R
R
R
R
$FE03
Register (SBFCR) Write:
See page 173. _{Reset: 0}
$FE04
Interrupt Status ^{Read: IF6}
IF5
IF4
IF3
IF2
IF1
0
0
Register 1 (INT1) Write: R
R
R
R
R
R
R
R
See page 167. _{Reset: 0}
0
0
0
0
0
0
0
$FE05
Interrupt Status ^{Read: IF14}
IF13
IF12
IF11
IF10
IF9
IF8
IF7
Register 2 (INT2) Write: R
R
R
R
R
R
R
R
See page 168. _{Reset: 0}
0
0
0
0
0
0
0
$FE06
Interrupt Status ^{Read: 0}
0
0
0
0
0
IF16
IF15
Register 3 (INT3) Write: R
R
R
R
R
R
R
R
See page 168. _{Reset: 0}
0
0
0
0
0
0
0
= Unimplemented
R = Reserved
Figure 14-2. SIM I/O Register Summary
MC68HC908GR8A • MC68HC908GR4A Data Sheet, Rev. 5
158
Freescale Semiconductor