MC68HC908GR8A_07 Datasheet, PDF (197/260 Pages) Freescale Semiconductor, Inc – Microcontrollers

Timebase Control Register
If the timebase functions are not required during stop mode, reduce power consumption by disabling the
timebase module before executing the STOP instruction.
16.6 Timebase Control Register
The timebase has one register, the timebase control register (TBCR), which is used to enable the
timebase interrupts and set the rate.
Address: $001C
Bit 7
Read: TBIF
Write:
Reset: 0
6
5
TBR2
TBR1
0
0
= Unimplemented
4
TBR0
0
3
0
TACK
0
R
2
TBIE
0
= Reserved
1
TBON
0
Bit 0
R
0
Figure 16-2. Timebase Control Register (TBCR)
TBIF — Timebase Interrupt Flag
This read-only flag bit is set when the timebase counter has rolled over.
1 = Timebase interrupt pending
0 = Timebase interrupt not pending
TBR2–TBR0 — Timebase Divider Selection Bits
These read/write bits select the tap in the counter to be used for timebase interrupts as shown in
Table 16-1.
Table 16-1. Timebase Divider Selection
TBR2
0
0
0
0
1
1
1
1
TBR1
0
0
1
1
0
0
1
1
TBR0
0
1
0
1
0
1
0
1
Divider
32,768
8192
2048
128
64
32
16
8
NOTE
Do not change TBR2–TBR0 bits while the timebase is enabled (TBON = 1).
TACK— Timebase Acknowledge Bit
The TACK bit is a write-only bit and always reads as 0. Writing a 1 to this bit clears TBIF, the timebase
interrupt flag bit. Writing a 0 to this bit has no effect.
1 = Clear timebase interrupt flag
0 = No effect
MC68HC908GR8A • MC68HC908GR4A Data Sheet, Rev. 5
Freescale Semiconductor
197