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MC68HC908GR8A_07 Datasheet, PDF (235/260 Pages) Freescale Semiconductor, Inc – Microcontrollers
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3.0 V DC Electrical Characteristics
Characteristic(1)
Symbol
Min
Typ(2)
Max
Unit
VDD supply current
Run(3)
Wait(4)
Stop(5)
Stop with TBM enabled(6)
Stop with LVI and TBM enabled(6)
Stop with LVI
I/O ports Hi-Z leakage current(7)
Input current
Pullup resistors (as input only)
Ports PTA3/KBD37–PTA0/KBD0, PTC1–PTC0,
PTD6/T2CH0–PTD0/SS
—
4.5
8
mA
—
1.65
4
mA
IDD
—
1
6
μA
—
300
500
μA
—
500
700
μA
—
200
300
μA
IIL
—
10
10
μA
IIn
—
—
1
μA
RPU
20
45
65
kΩ
Capacitance
Ports (as input or output)
COut
—
CIn
—
—
—
12
8
pF
Monitor mode entry voltage
VTST
VDD +2.5
—
8.5
V
Low-voltage inhibit, trip falling voltage – target
VTRIPF
2.35
2.60
2.70
V
Low-voltage inhibit, trip rising voltage – target
VTRIPR
2.45
2.66
2.80
V
Low-voltage inhibit reset/recover hysteresis – target
(VTRIPF + VHYS = VTRIPR)
POR rearm voltage(8)
POR reset voltage(9)
POR rise time ramp rate(10)
VHYS
—
60
VPOR
0
—
VPORRST
0
700
RPOR
0.02
—
—
mV
100
mV
800
mV
—
V/ms
1. VDD = 3.0 Vdc ± 10%, VSS = 0 Vdc, TA = TL to TH, unless otherwise noted
2. Typical values reflect average measurements at midpoint of voltage range, 25 °C only.
3. Run (operating) IDD measured using external square wave clock source (fosc = 16.4 MHz). All inputs 0.2 V from rail. No dc
loads. Less than 100 pF on all outputs. CL = 20 pF on OSC2. All ports configured as inputs. OSC2 capacitance linearly
affects run IDD. Measured with all modules enabled.
4. Wait IDD measured using external square wave clock source (fosc = 16.4 MHz). All inputs 0.2 V from rail. No dc loads. Less
than 100 pF on all outputs. CL = 20 pF on OSC2. All ports configured as inputs. OSC2 capacitance linearly affects wait
IDD. Measured with PLL and LVI enabled.
5. Stop IDD is measured with OSC1 = VSS.
6. Stop IDD with TBM enabled is measured using an external crystal clock source (fOSC = 4 MHz). All inputs 0.2 V from rail.
No dc loads. Less than 100 pF on all outputs. All inputs configured as inputs.
7. Pullups and pulldowns are disabled.
8. Maximum is highest voltage that POR is guaranteed.
9. Maximum is highest voltage that POR is possible.
10. If minimum VDD is not reached before the internal POR reset is released, RST must be driven low externally until minimum
VDD is reached.
MC68HC908GR8A • MC68HC908GR4A Data Sheet, Rev. 5
Freescale Semiconductor
235
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