MC68HC908GR8A_07 Datasheet, PDF (161/260 Pages) Freescale Semiconductor, Inc – Microcontrollers

IRST
RST
CGMXCLK
IAB
Reset and System Initialization
RST PULLED LOW BY MCU
32 CYCLES
32 CYCLES
Figure 14-5. Internal Reset Timing
VECTOR HIGH
ILLEGAL ADDRESS RST
ILLEGAL OPCODE RST
COPRST
LVI
INTERNAL RESET
POR
MODRST
Figure 14-6. Sources of Internal Reset
Table 14-2. Reset Recovery Type
Reset Recovery Type
POR/LVI
All others
Actual Number of Cycles
4163 (4096 + 64 + 3)
67 (64 + 3)
14.3.2.1 Power-On Reset
When power is first applied to the MCU, the power-on reset module (POR) generates a pulse to indicate
that power-on has occurred. The external reset pin (RST) is held low while the SIM counter counts out
4096 + 32 CGMXCLK cycles. Thirty-two CGMXCLK cycles later, the CPU and memories are released
from reset to allow the reset vector sequence to occur.
At power-on, these events occur:
• A POR pulse is generated.
• The internal reset signal is asserted.
• The SIM enables CGMOUT.
• Internal clocks to the CPU and modules are held inactive for 4096 CGMXCLK cycles to allow
stabilization of the oscillator.
• The RST pin is driven low during the oscillator stabilization time.
• The POR bit of the SIM reset status register (SRSR) is set and all other bits in the register are
cleared.
MC68HC908GR8A • MC68HC908GR4A Data Sheet, Rev. 5
Freescale Semiconductor
161