MC68HC908GR8A_07 Datasheet, PDF (118/260 Pages) Freescale Semiconductor, Inc – Microcontrollers

Input/Output (I/O) Ports
PTA3–PTA0 — Port A Data Bits
These read/write bits are software programmable. Data direction of each port A pin is under the control
of the corresponding bit in data direction register A. Reset has no effect on port A data.
KBD3–KBD0 — Keyboard Inputs
The keyboard interrupt enable bits, KBIE3–KBIE0, in the keyboard interrupt control register (KBICR)
enable the port A pins as external interrupt pins. See Chapter 9 Keyboard Interrupt Module (KBI).
12.2.2 Data Direction Register A
Data direction register A (DDRA) determines whether each port A pin is an input or an output. Writing a 1
to a DDRA bit enables the output buffer for the corresponding port A pin; a 0 disables the output buffer.
Address:
Read:
Write:
Reset:
$0004
Bit 7
0
0
6
5
0
0
0
0
= Unimplemented
4
3
2
1
Bit 0
0
DDRA3 DDRA2 DDRA1 DDRA0
0
0
0
0
0
Figure 12-3. Data Direction Register A (DDRA)
DDRA3–DDRA0 — Data Direction Register A Bits
These read/write bits control port A data direction. Reset clears DDRA3–DDRA0, configuring all port
A pins as inputs.
1 = Corresponding port A pin configured as output
0 = Corresponding port A pin configured as input
NOTE
Avoid glitches on port A pins by writing to the port A data register before
changing data direction register A bits from 0 to 1.
Figure 12-4 shows the port A I/O logic.
V_DD
READ DDRA ($0004)
WRITE DDRA ($0004)
RESET
WRITE PTA ($0000)
DDRAx
PTAx
PTAPUEx
INTERNAL
PULLUP
DEVICE
PTAx
READ PTA ($0000)
Figure 12-4. Port A I/O Circuit
MC68HC908GR8A • MC68HC908GR4A Data Sheet, Rev. 5
118
Freescale Semiconductor