MC68HC908GR8A_07 Datasheet, PDF (236/260 Pages) Freescale Semiconductor, Inc – Microcontrollers

Electrical Specifications
19.7 5.0 V Control Timing
Characteristic⁽¹⁾
Frequency of operation⁽²⁾
Crystal option
External clock option⁽³⁾
Symbol
f_osc
Min
1
dc⁽⁴⁾
Max
8
32.8
Unit
MHz
MHz
Internal operating frequency
Internal clock period (1/f_OP)
RESET input pulse width low⁽⁵⁾
IRQ interrupt pulse width low⁽⁶⁾ (edge-triggered)
IRQ interrupt pulse period
16-bit timer⁽⁷⁾
Input capture pulse width
Input capture period
f_op
—
8.2
t_cyc
122
—
t_IRL
50
—
t_ILIH
50
—
t_ILIL
Note 8
—
t_TH,t_TL
t_TLTL
Note 8
—
—
MHz
ns
ns
ns
t_cyc
ns
t_cyc
1. V_SS = 0 Vdc; timing shown with respect to 20% V_DD and 70% V_SS unless otherwise noted.
2. See 19.15 Clock Generation Module Characteristics for more information.
3. No more than 10% duty cycle deviation from 50%
4. Some modules may require a minimum frequency greater than dc for proper operation. See appropriate table for this
information.
5. Minimum pulse width reset is guaranteed to be recognized. It is possible for a smaller pulse width to cause a reset.
6. Minimum pulse width is for guaranteed interrupt. It is possible for a smaller pulse width to be recognized.
7. Minimum pulse width is for guaranteed interrupt. It is possible for a smaller pulse width to be recognized.
8. The minimum period, t_ILIL or t_TLTL, should not be less than the number of cycles it takes to execute the interrupt service
routine plus t_cyc.
19.8 3.0 V Control Timing
Characteristic⁽¹⁾
Frequency of operation⁽²⁾
Crystal option
External clock option⁽³⁾
Symbol
f_osc
Min
1
dc⁽⁴⁾
Max
8
16.4
Unit
MHz
MHz
Internal operating frequency
Internal clock period (1/f_OP)
RESET input pulse width low⁽⁵⁾
IRQ interrupt pulse width low⁽⁶⁾ (edge-triggered)
IRQ interrupt pulse period
16-bit timer⁽⁷⁾
Input capture pulse width
Input capture period
f_op
—
4.1
t_cyc
244
—
t_IRL
125
—
t_ILIH
125
—
t_ILIL
Note 8
—
t_TH,t_TL
t_TLTL
Note 8
—
—
MHz
ns
ns
ns
t_cyc
ns
t_cyc
1. V_SS = 0 Vdc; timing shown with respect to 20% V_DD and 70% V_SS unless otherwise noted.
2. See 19.15 Clock Generation Module Characteristics for more information.
3. No more than 10% duty cycle deviation from 50%
4. Some modules may require a minimum frequency greater than dc for proper operation. See appropriate table for this
information.
5. Minimum pulse width reset is guaranteed to be recognized. It is possible for a smaller pulse width to cause a reset.
6. Minimum pulse width is for guaranteed interrupt. It is possible for a smaller pulse width to be recognized.
7. Minimum pulse width is for guaranteed interrupt. It is possible for a smaller pulse width to be recognized.
8. The minimum period, t_ILIL or t_TLTL, should not be less than the number of cycles it takes to execute the interrupt service
routine plus t_cyc.
MC68HC908GR8A • MC68HC908GR4A Data Sheet, Rev. 5
236
Freescale Semiconductor