MC68HC908GR8A_07 Datasheet, PDF (214/260 Pages) Freescale Semiconductor, Inc – Microcontrollers

Timer Interface Module (TIM1 and TIM2)
17.9.5 TIM Channel Registers
These read/write registers contain the captured TIM counter value of the input capture function or the
output compare value of the output compare function. The state of the TIM channel registers after reset
is unknown.
In input capture mode (MSxB:MSxA = 0:0), reading the high byte of the TIM channel x registers (TCHxH)
inhibits input captures until the low byte (TCHxL) is read.
In output compare mode (MSxB:MSxA ≠ 0:0), writing to the high byte of the TIM channel x registers
(TCHxH) inhibits output compares until the low byte (TCHxL) is written.
See Figure 17-13 through Figure 17-16.
Address: T1CH0H, $0026 and T2CH0H, $0031
Bit 7
6
5
4
3
2
Read:
Bit 15
14
13
12
11
10
Write:
1
Bit 0
9
Bit 8
Reset:
Indeterminate after reset
Figure 17-13. TIM Channel 0 Register High (TCH0H)
Address: T1CH0L, $0027 and T2CH0L $0032
Bit 7
6
5
4
3
2
1
Bit 0
Read:
Bit 7
6
5
4
3
2
1
Bit 0
Write:
Reset:
Indeterminate after reset
Figure 17-14. TIM Channel 0 Register Low (TCH0L)
Address: T1CH1H, $0029
Bit 7
6
5
4
3
2
1
Bit 0
Read:
Bit 15
14
13
12
11
10
Write:
9
Bit 8
Reset:
Indeterminate after reset
Figure 17-15. TIM Channel 1 Register High (TCH1H)
Address: T1CH1L, $002A
Bit 7
6
5
4
3
2
1
Bit 0
Read:
Bit 7
6
5
4
3
2
1
Bit 0
Write:
Reset:
Indeterminate after reset
Figure 17-16. TIM Channel 1 Register Low (TCH1L)
MC68HC908GR8A • MC68HC908GR4A Data Sheet, Rev. 5
214
Freescale Semiconductor