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MC68HC908GR8A_07 Datasheet, PDF (203/260 Pages) Freescale Semiconductor, Inc – Microcontrollers
Functional Description
Addr.
Register Name
Bit 7
6
5
4
3
2
Timer 2 Counter Read: Bit 15
14
13
12
11
10
$002C Register High (T2CNTH) Write:
See page 210. Reset:
0
0
0
0
0
0
Timer 2 Counter Read: Bit 7
6
5
4
3
2
$002D
Register Low (T2CNTL) Write:
See page 210. Reset:
0
0
0
0
0
0
Timer 2 Counter Modulo Read: Bit 15
14
13
12
11
10
$002E Register High (T2MODH) Write:
See page 211. Reset:
1
1
1
1
1
1
Timer 2 Counter Modulo Read: Bit 7
6
5
4
3
2
$002F Register Low (T2MODL) Write:
See page 211. Reset:
1
1
1
1
1
1
Timer 2 Channel 0 Status and Read:
$0030 Control Register (T2SC0) Write:
See page 211. Reset:
CH0F
0
0
CH0IE
0
MS0B
0
MS0A
0
ELS0B
0
ELS0A
0
Timer 2 Channel 0 Read: Bit 15
14
$0031 Register High (T2CH0H) Write:
See page 214. Reset:
13
12
11
10
Indeterminate after reset
Timer 2 Channel 0 Read: Bit 7
6
$0032
Register Low (T2CH0L) Write:
See page 214. Reset:
5
4
3
2
Indeterminate after reset
$0033
Read:
R
R
R
R
R
R
Reserved Write:
Reset: 0
0
0
0
0
0
$0034
↓
$0035
Read:
R
R
R
R
R
R
Reserved Write:
Reset:
Indeterminate after reset
= Unimplemented
Figure 17-3. TIM I/O Register Summary (Sheet 2 of 2)
1
Bit 0
9
Bit 8
0
0
1
Bit 0
0
9
1
1
1
TOV0
0
9
0
Bit 8
1
Bit 0
1
CH0MAX
0
Bit 8
1
Bit 0
R
R
0
0
R
R
17.4.1 TIM Counter Prescaler
The TIM clock source can be one of the seven prescaler outputs. The prescaler generates seven clock
rates from the internal bus clock. The prescaler select bits, PS[2:0], in the TIM status and control register
select the TIM clock source.
17.4.2 Input Capture
With the input capture function, the TIM can capture the time at which an external event occurs. When an
active edge occurs on the pin of an input capture channel, the TIM latches the contents of the TIM counter
into the TIM channel registers, TCHxH:TCHxL. The polarity of the active edge is programmable. Input
captures can generate TIM CPU interrupt requests.
MC68HC908GR8A • MC68HC908GR4A Data Sheet, Rev. 5
Freescale Semiconductor
203