MC68HC908GR8A_07 Datasheet, PDF (168/260 Pages) Freescale Semiconductor, Inc – Microcontrollers

System Integration Module (SIM)
Interrupt Status Register 2
Address: $FE05
Bit 7
6
5
4
3
2
1
Bit 0
Read: I14
I13
I12
I11
I10
I9
I8
I7
Write: R
R
R
R
R
R
R
R
Reset: 0
0
0
0
0
0
0
0
R
= Reserved
Figure 14-13. Interrupt Status Register 2 (INT2)
I14–I7 — Interrupt Flags 14–7
These flags indicate the presence of interrupt requests from the sources shown in Table 14-3.
1 = Interrupt request present
0 = No interrupt request present
Interrupt Status Register 3
Address: $FE06
Bit 7
6
5
4
3
2
1
Bit 0
Read: 0
0
0
0
0
0
I16
I15
Write: R
R
R
R
R
R
R
R
Reset: 0
0
0
0
0
0
0
0
R
= Reserved
Figure 14-14. Interrupt Status Register 3 (INT3)
Bits 7–6 — Always read 0
I16 and I15 — Interrupt Flags 16 and 15
These flags indicate the presence of an interrupt request from the source shown in Table 14-3.
1 = Interrupt request present
0 = No interrupt request present
14.5.2 Reset
All reset sources always have equal and highest priority and cannot be arbitrated.
14.5.3 Break Interrupts
The break module can stop normal program flow at a software-programmable break point by asserting
its break interrupt output (see Chapter 17 Timer Interface Module (TIM1 and TIM2)). The SIM puts the
CPU into the break state by forcing it to the SWI vector location. Refer to the break interrupt subsection
of each module to see how each module is affected by the break state.
14.5.4 Status Flag Protection in Break Mode
The SIM controls whether status flags contained in other modules can be cleared during break mode. The
user can select whether flags are protected from being cleared by properly initializing the break clear flag
enable bit (BCFE) in the SIM break flag control register (SBFCR).
MC68HC908GR8A • MC68HC908GR4A Data Sheet, Rev. 5
168
Freescale Semiconductor