MC68HC908GR8A_07 Datasheet, PDF (226/260 Pages) Freescale Semiconductor, Inc – Microcontrollers

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18.3.1.4 Data Format
Communication with the monitor ROM is in standard non-return-to-zero (NRZ) mark/space data format.
Transmit and receive baud rates must be identical.
START
BIT BIT 0
BIT 1 BIT 2 BIT 3 BIT 4 BIT 5
NEXT
START
BIT 6 BIT 7 STOP BIT
BIT
Figure 18-12. Monitor Data Format
18.3.1.5 Break Signal
A start bit (0) followed by nine 0 bits is a break signal. When the monitor receives a break signal, it drives
the PTA0 pin high for the duration of approximately two bits and then echoes back the break signal.
MISSING STOP BIT
APPROXIMATELY 2 BITS DELAY
BEFORE ZERO ECHO
01234567
01234567
Figure 18-13. Break Transaction
18.3.1.6 Baud Rate
The communication baud rate is controlled by the crystal frequency or external clock and the state of the
PTB4 pin (when IRQ is set to V_TST) upon entry into monitor mode. If monitor mode was entered with V_DD
on IRQ and the reset vector blank, then the baud rate is independent of PTB4.
Table 18-1 also lists external frequencies required to achieve a standard baud rate of 9600 bps. The
effective baud rate is the bus frequency divided by 256. If using a crystal as the clock source, be aware
of the upper frequency limit that the internal clock module can handle. See 19.5 5.0 V DC Electrical
Characteristics or 19.6 3.0 V DC Electrical Characteristics for this limit.
18.3.1.7 Commands
The monitor ROM firmware uses these commands:
• READ (read memory)
• WRITE (write memory)
• IREAD (indexed read)
• IWRITE (indexed write)
• READSP (read stack pointer)
• RUN (run user program)
The monitor ROM firmware echoes each received byte back to the PTA0 pin for error checking. An 11-bit
delay at the end of each command allows the host to send a break character to cancel the command. A
delay of two bit times occurs before each echo and before READ, IREAD, or READSP data is returned.
The data returned by a read command appears after the echo of the last byte of the command.
NOTE
Wait one bit time after each echo before sending the next byte.
MC68HC908GR8A • MC68HC908GR4A Data Sheet, Rev. 5
226
Freescale Semiconductor