MC68HC908GR8A_07 Datasheet, PDF (164/260 Pages) Freescale Semiconductor, Inc – Microcontrollers

System Integration Module (SIM)
14.5.1 Interrupts
At the beginning of an interrupt, the CPU saves the CPU register contents on the stack and sets the
interrupt mask (I bit) to prevent additional interrupts. At the end of an interrupt, the RTI instruction recovers
the CPU register contents from the stack so that normal processing can resume. Figure 14-8 shows
interrupt entry timing. Figure 14-9 shows interrupt recovery timing.
MODULE
INTERRUPT
I BIT
IAB
IDB
R/W
DUMMY
SP
SP – 1 SP – 2 SP – 3 SP – 4 VECT H VECT L START ADDR
DUMMY PC – 1[7:0] PC – 1[15:8] X
A
CCR V DATA H V DATA L OPCODE
Figure 14-8. Interrupt Entry Timing
MODULE
INTERRUPT
I BIT
IAB
IDB
R/W
SP – 4 SP – 3 SP – 2 SP – 1
SP
PC
PC + 1
CCR
A
X PC – 1 [7:0] PC – 1 [15:8] OPCODE OPERAND
Figure 14-9. Interrupt Recovery Timing
MC68HC908GR8A • MC68HC908GR4A Data Sheet, Rev. 5
164
Freescale Semiconductor