XRT79L71_07 Datasheet, PDF (87/109 Pages) Exar Corporation – 1-CHANNEL DS3/E3 ATM UNI/PPP/CLEAR-CHANNEL FRAMER IC - HARDWARE

REV. 1.0.0
XRT79L71
1-CHANNEL DS3/E3 ATM UNI/PPP/CLEAR-CHANNEL FRAMER IC - HARDWARE
TABLE 9: TIMING INFORMATION FOR THE MICROPROCESSOR INTERFACE WHEN CONFIGURED TO OPERATE IN THE
MOTOROLA (68K) ASYNCHRONOUS MODE
Test Conditions: TA = 25°C, VCC = 3.3V±5% and 2.5V±5%, unless otherwise specified.
TIMING
DESCRIPTION
MIN.
TYP.
MAX
t0
Address setup time to pALE low
6
-
-
t1
Address hold time to pALE high
6
-
-
t2
Data setup time to pDS_L low
0
-
-
t3
Data hold time to pDS_L low
160
-
-
t4
pDS_L high to pRDY_L high (Write Cycle)
-
-
16
t5
pRDY_L low to Data valid
-
-
15
t6
pDS_L high to pRDY_L high (Read Cycle)
-
-
16
t7
pRDY_L high to Data invalid
3
-
-
MICROPROCESSOR INTERFACE TIMING - POWER PC 403 SYNCHRONOUS MODE
FIGURE 10. SYNCHRONOUS MODE 3 - IBM POWERPC 403 INTERFACE TIMING (WRITE CYCLE)
pCLK
pCS_L
pRW_L
pA[14:0]
pD[7:0]
pWE_L
pOE_L
pRdy
t0
t1
t2
Address
t3
t4
Data
t5
t6
t7
t8
t9
NOTE: The value for "t0" through "t12" can be found in Table 10.
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