XRT79L71_07 Datasheet, PDF (40/109 Pages) Exar Corporation – 1-CHANNEL DS3/E3 ATM UNI/PPP/CLEAR-CHANNEL FRAMER IC - HARDWARE

XRT79L71
1-CHANNEL DS3/E3 ATM UNI/PPP/CLEAR-CHANNEL FRAMER IC - HARDWARE
REV. 1.0.0
PIN #
D5
A2
C5
NAME
RxPOOF
RxPLOF
RxNib_0/
RxHDLCDat_0
TYPE
O
O
O
DESCRIPTION
Receive PLCP Processor Block - PLCP Out of Frame Defect Indicator:
The XRT79L71 will assert this output pin (e.g., toggle it "High") anytime (and for
the duration that) the Receive PLCP Processor block is currently declaring the
PLCP OOF (Out of Frame) defect condition.
Conversely, the XRT79L71 will negate this output pin (e.g., toggle it "Low") any-
time (and for the duration that) the Receive PLCP Processor block is NOT
declaring the PLCP OOF defect condition.
NOTE: This output pin is only active if the XRT79L71 has been configured to
operate in both the ATM UNI and PLCP Modes.
Receive PLCP Processor Block - PLCP Loss of Frame Defect Indicator
Output:
The XRT79L71 will assert this output pin (e.g., toggle it "High") anytime (and for
the duration that) the Receive PLCP Processor block is currently declaring the
PLCP LOF (Loss of Frame) defect condition.
Conversely, the XRT79L71 will negate this output pin (e.g., toggle it "Low") any-
time (and for the duration that) the Receive PLCP Processor block is NOT
declaring the PLCP LOF defect condition.
NOTE: This output pin is only active is the XRT79L71 has been configured to
operate in both the ATM UNI/PLCP Modes.
Receive Nibble Interface Output pin - Bit 0/Receive HDLC Controller Data
Bus output pin - Bit 0:
The function of this output pin depends upon whether the XRT79L71 has been
configured to operate in the Clear-Channel/Nibble-Parallel Mode, the High-
Speed HDLC Controller Mode, or in some other mode.
Clear-Channel/Nibble-Parallel Mode - RxNib_0:
The XRT79L71 will output Received data from the remote terminal equipment
to the System-Side terminal equipment via this pin, along with RxNib_1 through
RxNib_3. This particular output pin functions as the LSB.
The data at this pin is updated on the rising edge of the RxClk output signal.
Hence, the user's System-Side terminal equipment should sample this signal
upon the falling edge of RxClk.
High-Speed HDLC Controller Mode - Receive High-Speed HDLC Controller
Output Interface Block - Data Bus Output Pin #0 - RxHDLCDat_0:
This output pin along with RxHDLCDat_[7:1] functions as the Receive High-
Speed HDLC Controller Output Interface byte wide output data bus. This par-
ticular output pin functions as the LSB (Least Significant Bit) of the Receive
High-Speed HDLC Controller byte wide data bus. The Receive High-Speed
HDLC Controller will output the contents of all HDLC frames and flag sequence
octects via this output data bus, upon the rising edge of the RxHDLCClk output
signal. Hence, the user's System-Side terminal equipment should be designed/
configured to sample this data upon the falling edge of the RxHDLCClk output
clock signal.
NOTE: This output pin is only active if the XRT79L71 is configured to operate in
either the Clear-Channel/ Framer/Nibble-Parallel Mode or in the High-
Speed HDLC Controller Mode. This output is inactive for all remaining
modes.
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