XRT79L71_07 Datasheet, PDF (33/109 Pages) Exar Corporation – 1-CHANNEL DS3/E3 ATM UNI/PPP/CLEAR-CHANNEL FRAMER IC - HARDWARE

REV. 1.0.0
PIN #
L4
NAME
TxTSX/
TxPSOF
P1
TxUClkO/
TxPClkO
M1
TxUClk/
TxPClk
XRT79L71
1-CHANNEL DS3/E3 ATM UNI/PPP/CLEAR-CHANNEL FRAMER IC - HARDWARE
TYPE
DESCRIPTION
I Transmit - Change of Port Indicator Input/Transmit - Start of PPP Packet in
Chunk Mode:
The function of this input pin depends upon whether the XRT79L71 has been
configured to operate in the Packet Mode or Cell-Chunk Mode.
Packet Mode - TxTSX TxTSX - Transmit POS-PHY Interface - Change of
Port Indicator Output (POS-PHY Level 3, Packet Mode only):
The Link-Layer processor pulses this input pin "High" when an in-band port
address is present on the TxPData[15:11] bus input pins. When this input pin
and TxPENB are both set "High" then the value of TxPData[15:11] is the
address value of the TxFIFO (Transmit POS-PHY Port) to be selected. Subse-
quent write operations, into TxPData[15:0] will fill the TxFIFO (within the Trans-
mit POS-PHY Port) corresponding to this particular in-band address.
Chunk Mode - TxPSOF - Transmit Start of Packet Input Indicator:
The Link Layer processor pulses this input pin "High" in order to indicate that the
first byte (or 16-bit word) of a given Packet is placed on the TxPData[15:0] pins.
NOTE:
This input pin is only active if the XRT79L71 has been configured to
operate in the POS-PHY Level 3, Packet Mode or in the Chunk Mode. If
the user intends to operate the XRT79L71 in any other mode, then the
user should tie this input pin to GND.
O Transmit UTOPIA Interface Clock/Transmit POS-PHY Interface Clock Out-
put:
This output is derived from an internal PLL.
I Transmit UTOPIA Interface Clock/Transmit POS-PHY Interface Clock Input:
The function of this input pin depends upon whether the XRT79L71 has been
configured to operate in the ATM UNI or in the PPP Mode.
ATM UNI Mode - TxUClk - Transmit UTOPIA Interface - Clock Input pin:
The Transmit UTOPIA Interface clock is used to latch the data on the Transmit
UTOPIA Data bus, into the Transmit UTOPIA Interface block. This clock signal
is also used as the timing source for circuitry used to process the ATM cell data
into and through the TxFIFO.
During Multi-PHY operation, the data on the Transmit UTOPIA Address bus pins
is sampled on the rising edge of TxUClk.
PPP Mode - TxPClk - Transmit POS-PHY Interface - Clock Input pin:
The Transmit POS-PHY Interface clock is used to latch the data on the Transmit
POS-PHY Data bus, into the Transmit POS-PHY Interface block. This clock sig-
nal is also used as the timing source for circuitry used to process the Packet data
into and through the TxFIFO.
NOTES:
1. The XRT79L71 can support TxUClk or TxPClk clock frequencies of up
to 50MHz.
2. This input pin is inactive and should be tied to GND if the user
configures the XRT79L71 to operate in either the Clear-Channel
Framer or in the High-Speed HDLC Controller Modes.
30