XRT79L71_07 Datasheet, PDF (26/109 Pages) Exar Corporation – 1-CHANNEL DS3/E3 ATM UNI/PPP/CLEAR-CHANNEL FRAMER IC - HARDWARE

XRT79L71
1-CHANNEL DS3/E3 ATM UNI/PPP/CLEAR-CHANNEL FRAMER IC - HARDWARE
REV. 1.0.0
PIN #
A9
NAME
TxNib_0/
TxGFC/
TxHDLCDat_0
TYPE
DESCRIPTION
I Transmit Nibble Interface - Bit 0/Transmit GFC Input pin/Transmit HDLC
Controller Data Bus - Bit 0 Input:
The function of this input pin depends upon whether the XRT79L71 is configured
to operate in the Clear-Channel Framer Mode, the High Speed HDLC Controller
Mode or in the ATM Mode.
Clear-Channel Framer Mode - TxNib_0 - Transmit Nibble Interface - Bit 0:
If the XRT79L71 is configured to operate in the Nibble-Parallel Mode, then this
input pin will function as the bit 0 (LSB) input to the Transmit Nibble-Parallel input
interface. The Transmit Payload Data Input Interface block will sample this sig-
nal (along with TxNib_1 through TxNib_3) upon the falling edge of TxNibClk.
NOTE: This input pin is inactive if the XRT79L71 is configured to operate in the
Serial Mode.
ATM Mode - TxGFC TxGFC - Transmit GFC Port Input pin:
This signal, along with TxGFCMSB, and TxGFCClk combine to function as the
Transmit GFC Nibble Field serial input port. The user will specify the value of the
GFC field, within a given ATM cell, by serially transmitting its four bit-value into
this input pin. Each of these four bits will be clocked into the port upon the rising
edge of the TxGFCClk output signal.
High-Speed HDLC Controller Mode - TxHDLCDat_0 - Transmit HDLC Con-
troller Data Bus - Bit 0 Input pin:
If the XRT79L71 is configured to operate in the High-Speed HDLC Controller
mode, then this input pin will function as Bit 0 (the LSB) within the Transmit High-
Speed HDLC Controller Input Interface block - Input Data Bus (e.g., the TxHDL-
CData[7:0] input pins).
The Transmit High-Speed HDLC Controller Input Interface block provides the
System-Side terminal equipment with a byte-wide Transmit HDLC Controller
clock output signal (TxHDLCClk). The Transmit High-Speed HDLC Controller
Input Interface block samples the data residing on this input pin (along with the
rest of the TxHDLCData[7:0] input pins) upon the rising edge of the TxHDLCClk
clock output signal.
NOTE: This input pin is inactive and should be tied to GND if the XRT79L71 has
been configured to operate in the PPP Mode.
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