XRT79L71_07 Datasheet, PDF (39/109 Pages) Exar Corporation – 1-CHANNEL DS3/E3 ATM UNI/PPP/CLEAR-CHANNEL FRAMER IC - HARDWARE

REV. 1.0.0
PIN #
B5
NAME
RxLCD/
RxOutClk/
RxHDLCDat_7
D7
RxLOS
B2
RxPRED
XRT79L71
1-CHANNEL DS3/E3 ATM UNI/PPP/CLEAR-CHANNEL FRAMER IC - HARDWARE
TYPE
O
O
O
DESCRIPTION
Receive Loss of Cell Delineation Defect indicator/Receive Output Clock
signal/Receive HDLC Controller Data Bus - Bit 7 Output:
The function of output pin depends upon whether the XRT79L71 has been con-
figured to operate in the ATM, Clear-Channel Framer or High Speed HDLC
Controller Mode.
ATM Mode - RxLCD:(Loss of Cell Delineation Defect Indicator)
The XRT79L71 will assert this output pin (e.g., toggle it "High") anytime (and for
the duration that) the Receive ATM Cell Processor block is declaring the LCD
(Loss of Cell Delineation) defect condition. The XRT79L71 will negate this out-
put pin (e.g., toggle it "Low") whenever the Receive ATM Cell Processor block is
not currently declaring the LCD defect condition.
Clear-Channel Framer Mode - RxOutClk:
This clock signal functions as the Transmit Payload Data Input Interface clock
source, if the XRT79L71 has been configured to operate in the loop-timing
mode.
In this mode, the System-Side terminal equipment is expected to input data to
the TxSer input pin, upon the rising edge of this clock signal. The XRT79L71
will use the rising edge of this signal to sample the data on the TxSer input.
High-Speed HDLC Controller Mode - Receive High-Speed HDLC Controller
Output Interface Block - Data Bus Output Pin #7 - RxHDLCDat_7:
This output pin along with RxHDLCDat_[6:0] functions as the Receive High-
Speed HDLC Controller Output Interface byte wide output data bus. This partic-
ular output pin functions as the MSB (Most Significant Bit) of the Receive High-
Speed HDLC Controller Output Interface byte wide data bus. The Receive
High-Speed HDLC Controller Output Interface block will output the contents of
all HDLC frames and flag sequence octets via this output data bus, upon the ris-
ing edge of the RxHDLCClk output signal. Hence, the user's System-Side ter-
minal equipment should be designed/configured to sample this data upon the
falling edge of the RxHDLCClk output clock signal.
LOS (Loss of Signal) Defect Indicator:
The XRT79L71 will assert this output pin (e.g., toggle it "High") anytime (and for
the duration that) the Receive DS3/E3 Framer block declares the LOS defect
condition.
Conversely, the XRT79L71 will negate this output pin (e.g., toggle it "Low") any-
time (and for the duration that) the Receive DS3/E3 Framer block is NOT
declaring the LOS defect condition.
Receiver Red Alarm Indicator - Receive PLCP Processor:
The XRT79L71 will assert this output pin (e.g., toggle it "High") anytime (and for
the duration that) the Receive PLCP Processor block is currently declaring any
of the following defect conditions.
• PLCP OOF - PLCP Out of Frame Defect Condition
• PLCP LOF - PLCP Loss of Frame Defect Condition
Conversely, the XRT79L71 will negate this output pin (e.g., toggle it "Low") any-
time (and for the duration that) the Receive PLCP Processor block is NOT
declaring any of the above-mentioned defect conditions.
NOTE: This output pin is only active if the XRT79L71 has been configured to
operate in both the ATM UNI and PLCP Modes..
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