XRT79L71_07 Datasheet, PDF (66/109 Pages) Exar Corporation – 1-CHANNEL DS3/E3 ATM UNI/PPP/CLEAR-CHANNEL FRAMER IC - HARDWARE

XRT79L71
1-CHANNEL DS3/E3 ATM UNI/PPP/CLEAR-CHANNEL FRAMER IC - HARDWARE
REV. 1.0.0
c. To comply with the Category I and II Jitter Tolerance Requirements per Bellcore GR-499-CORE (for DS3
Applications)
d. To comply with the Jitter Tolerance Requirements per ITU-T G.823 (for E3 Applications)
e. To comply with the Interference Margin Requirements of 20dB, per ITU-T G.703 (for E3 Applications)
The Receive DS3/E3 Framer Block
The purpose of the Receive DS3/E3 Framer block is to acquire and maintain Frame Synchronization with the
incoming DS3/E3 data-stream that it receives from the Receive DS3/E3 LIU Block. As the Receive DS3/E3
Framer block performs this task, it will also do the following.
• It will declare and clear the LOS defect condition
• It will declare and clear the LOF/OOF defect condition
• It will declare and clear the AIS defect condition
• It will declare and clear the FERF/RDI defect condition
• It will detect and flag the occurrences of P-bit, CP-bit and Framing bit errors (DS3 Applications)
• It will detect and flag the occurrence of BIP-8 Errors (E3, ITU-T G.832 Applications)
• It will detect and flag the occurrence of BIP-4 Errors (E3, ITU-T G.751 Applications)
• It will detect and flag the occurrence of FEBE/REI Events
• It will route all PMDL data to the Receive LAPD Controller block for further processing
• It will route all DS3/E3 payload to the Receive High-Speed HDLC Controller block.
The Receive Trail-Trace Message Controller Block (E3, ITU-T G.832 Applications only)
The Receive SSM Controller Block (E3, ITU-T G.832 Applications only)
The Receive FEAC Controller Block (DS3 Applications only)
The purpose of the Receive FEAC Controller block is to permit the user to receive FEAC (Far-End Alarm &
Control) Messages from the remote terminal equipment.
NOTE: The Receive FEAC Controller block is only active if the XRT79L71 is configured to operate in the DS3, C-bit Parity
Framing format.
The Receive LAPD Controller Block
The purpose of the Receive LAPD Controller block is to permit the user to receive LAPD/PMDL (Path
Maintenance Data Link) Messages from the remote terminal equipment. The Receive LAPD Controller block
comes with a Receive LAPD Controller (not to be confused with the Receive High-Speed HDLC Controller
block) and 90 bytes of on-chip RAM (for storage of inbound PMDL Messages) after reception.
The Receive High-Speed HDLC Controller Block
The purpose of the Receive High-Speed HDLC Controller block is to receive the payload data (from the
incoming DS3/E3 data-stream) and perform the following tasks.
• To identify the boundaries of incoming HDLC frames (within the incoming DS3/E3 data-stream)
• To terminate the Flag Sequence octets within the incoming data-stream
• To (optionally) compute and verify the CRC-16 or CRC-32 values that have been appended to the back-end
of these incoming HDLC frames (at the remote terminal equipment) and to flag any occurrences of CRC
errors
• To zero-un-stuff the contents within these incoming HDLC frames
• To output this HDLC frame data (in a byte-wide manner) via an 8-bit wide Output Data Bus.
The Receive Overhead Data Output Interface Block (not shown in Figure 3).
63