XRT79L71_07 Datasheet, PDF (76/109 Pages) Exar Corporation – 1-CHANNEL DS3/E3 ATM UNI/PPP/CLEAR-CHANNEL FRAMER IC - HARDWARE

XRT79L71
1-CHANNEL DS3/E3 ATM UNI/PPP/CLEAR-CHANNEL FRAMER IC - HARDWARE
REV. 1.0.0
The Receive POS-PHY Interface Block
The purpose of the Receive POS-PHY Interface block is to provide a standard Saturn POS-PHY™ Level 2 or 3
compliant interface to the Link Layer Processor, for reading in the contents of all inbound PPP Packets, from
the Receive FIFO (RxFIFO).
The Receive POS-PHY Interface block can be configured to operate with either an 8 or 16-bit wide Receive
POS-PHY Data Bus.
NOTES:
1. The Receive POS-PHY Interface Block supports POS-PHY Level 3 from a signaling stand-point. The Receive
POS-PHY Interface block (within the XRT79L71) still only supports a 16-bit wide (not 32-bit wide) POS-PHY Data
Bus and only operates up to 50MHz (not 104MHz).
2. The Receive POS-PHY Interface Block can be configured to support either Out-of-Band Addressing or In-Band
Addressing for Device Selection to READ. However, since the XRT79L71 is a single-channel device, we strongly
recommend that the user only use Out-of-Band Addressing for Device Selection whenever it is designed into a
Multi-PHY systemin which multiple PHY Layer devices are sharing the same POS-PHY Bus.
A MORE DETAILED FUNCTIONAL/ARCHITECTURAL DESCRIPTION FOR THE PPP MODE
The Functional/Architectural Description of the XRT79L71, when configured to operate in the PPP Mode can
be found in Section _, within this document.
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4.0 INTERRUPT STRUCTURE WITHIN THE XRT79L71
The XRT79L71 is equipped with a sophisticated Interrupt Servicing Structure. This Interrupt Structure includes
an Interrupt Request output pin (INT*), numerous Interrupt Enable Registers and numerous Interrupt Status
Registers. The Interrupt Servicing Structure, within the XRT79L71 IC contains two levels of hierarchy. The top
level is at the Functional Block level (e.g., the Receive ATM Cell Processor Block, the Receive PPP Packet
Processor Block, the Receive DS3/E3 Framer block, etc). The lower hierarchical level is at the individual or
source level. Each hierarchical level consists of a complete set of Interrupt Status Registers/bits and Interrupt
Enable Registers/bits, as will be discussed below.
Most of the functional blocks within the XRT79L71 are capable of generating Interrupt Requests to the µC/µP.
The XRT79L71 Interrupt Structure has been carefully designed to allow the user to quickly determine the exact
source of the interrupt (with a minimum number of read operations, and, in-turn, minimal latency) which will aid
the µC/µP in determine the appropriate interrupt service routine to call up in order to either eliminate, or
properly respond to the condition(s) causing the interrupt.
Table 3 lists all of the possible conditions that can generate interrupts, within each functional block of the
XRT79L71.
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