XRT79L71_07 Datasheet, PDF (28/109 Pages) Exar Corporation – 1-CHANNEL DS3/E3 ATM UNI/PPP/CLEAR-CHANNEL FRAMER IC - HARDWARE

XRT79L71
1-CHANNEL DS3/E3 ATM UNI/PPP/CLEAR-CHANNEL FRAMER IC - HARDWARE
REV. 1.0.0
PIN #
M2
N1
NAME
TxPERR
TxPEOP
TYPE
DESCRIPTION
I Transmit POS-PHY Interface - Transmit Packet Error Indicator from Link
Layer:
The Link Layer Processor is expected to assert this input signal (e.g., toggle it
"High") anytime it is routing a packet to the Transmit POS-PHY Interface that is
erred and needs to be ABORTED. The Link Layer Processor should only assert
this input pin coincident to when the last byte, or 16-bit word, of a given packet is
being written onto the Transmit POS-PHY Data Bus (e.g., the TxPData[15:0])
input pins.
If the Link Layer Processor identifies a given outbound PPP Packet as being
erred, then the Transmit PPP Packet Processor block transmits this particular
packet to the remote terminal equipment as an Aborted Packet.
NOTE:
This input pin is only active if the XRT79L71 has been configured to
operate in the PPP Mode. The user should tie this input pin to GND if
the user intends to operate the XRT79L71 in some mode other than the
PPP Mode.
I Transmit POS-PHY Interface - End of Packet:
The link layer processor toggles this output pin "High" whenever the Link Layer
Processor is writing the last byte (or 16-bit word) of a given Packet into the
Transmit POS-PHY Data Bus (e.g., the TxPData[15:0] input pins).
NOTES:
1. This input pin is only valid when the XRT79L71 is configured to operate
in the PPP Mode. The user should tie this input pin to GND if the user
intends to operate the XRT79L71 in some mode other than the PPP
Mode.
2. This input pin is only valid when the Transmit POS-PHY Interface -
Write Enable Input pin (TxPEn) is asserted.
25