XRT79L71_07 Datasheet, PDF (24/109 Pages) Exar Corporation – 1-CHANNEL DS3/E3 ATM UNI/PPP/CLEAR-CHANNEL FRAMER IC - HARDWARE

XRT79L71
1-CHANNEL DS3/E3 ATM UNI/PPP/CLEAR-CHANNEL FRAMER IC - HARDWARE
REV. 1.0.0
PIN #
C8
NAME
TxNib_2/
TxStuff_Ctl/
TxHDLCDat_2
TYPE
DESCRIPTION
I Transmit Nibble Input Interface - Bit 2/Transmit PLCP Stuff Control Input/
Transmit HDLC Controller Data Bus - Bit 2 Input:
The function of this input pin depends upon whether the XRT79L71 is configured
to operate in the Clear-Channel Framer Mode, the High-Speed HDLC Controller
Mode, or in the ATM/PLCP Mode.
Clear-Channel Framer Mode - TxNib_2 - Transmit Nibble Interface - Bit 2:
If the XRT79L71 is configured to operate in the Nibble-Parallel Mode, then this
input pin will function as the bit 1 input to the Transmit Nibble-Parallel input inter-
face. The Transmit Payload Data Input Interface block will sample this signal
(along with TxNib_0, TxNib_2 and TxNib_3) upon the falling edge of TxNibClk
NOTE: This input pin is inactive if the XRT79L71 is configured to operate in the
Serial Mode.
ATM/PLCP Mode - TxStuff_Ctl - Transmit PLCP Stuff Control Input pin:
This input pin is used to externally exercise or forego trailer nibble stuffing oppor-
tunities by the Transmit PLCP Processor block. PLCP trailer nibble stuff oppor-
tunities occur in periods of three PLCP frames (375 us). The first PLCP frame
(first, within a stuff opportunity period) will have 13 trailer nibbles appended to it.
The second PLCP frame (second within a stuff opportunity period will have 14
trailer nibbles appended to it. The third PLCP frame (the location of the stuff
opportunity) will contain 13 trailer nibbles if this input pin is pulled "Low", and 14
trailer nibbles if this input pin is pulled "High".
NOTE: This input pin is inactive (and should be tied to GND) if the XRT79L71 is
configured to operate in the Direct-Mapped ATM Mode.
High-Speed HDLC Controller Mode - TxHDLCDat_2 - Transmit High-Speed
HDLC Controller Data Bus - Bit 2 Input pin:
If the XRT79L71 is configured to operate in the High-Speed HDLC Controller
mode, then this input pin will function as Bit 2 within the Transmit High-Speed
HDLC Controller Input Interface block - Input Data Bus (e.g., the TxHDL-
CData[7:0] input pins).
The Transmit High-Speed HDLC Controller Input Interface block provides the
System-Side terminal equipment with a byte-wide Transmit HDLC Controller
clock output signal (TxHDLCClk). The Transmit High-Speed HDLC Controller
Input Interface block samples the data residing on this input pin (along with the
rest of the TxHDLCData[7:0] input pins) upon the rising edge of the TxHDLCClk
clock output signal.
NOTE: This input pin is inactive (and should be tied to GND) if the XRT79L71
has been configured to operate in the PPP Mode.
21