XRT79L71_07 Datasheet, PDF (38/109 Pages) Exar Corporation – 1-CHANNEL DS3/E3 ATM UNI/PPP/CLEAR-CHANNEL FRAMER IC - HARDWARE

XRT79L71
1-CHANNEL DS3/E3 ATM UNI/PPP/CLEAR-CHANNEL FRAMER IC - HARDWARE
REV. 1.0.0
PIN #
D6
NAME
RxOOF/
RxNib_1/
RxHDLCDat_1
TYPE
O
DESCRIPTION
Receive Out of Frame Defect Indicator/Receive Nibble Interface Output pin
- Bit 1/Receive HDLC Controller Data Bus Output pin - Bit 1:
The function of this output pin depends upon whether the XRT79L71 has been
configured to operate in the Clear-Channel Framer/Nibble-Parallel Mode or the
High-Speed HDLC Controller Mode.
Clear-Channel Framer/Nibble-Parallel Mode - RxNib_1:
The XRT79L71 will output Received data from the remote terminal equipment
to the System-Side terminal equipment via this pin, along with RxNib_0,
RxNib_2 and RxNib_3: This particular output pin functions as the LSB. The
data at this pin is updated on the rising edge of the RxClk output signal. Hence,
the user's System-Side terminal equipment should sample this signal upon the
falling edge of RxClk.
High-Speed HDLC Controller Mode - Receive High Speed HDLC Controller
Output Interface Block - Data Bus Output Pin #1 - RxHDLCDat_1:
This output pin along with RxHDLCDat_[7:2] and RxHDLCDat_0 functions as
the Receive High-Speed HDLC Controller Output Interface byte wide output
data bus. The Receive High-Speed HDLC Controller will output the contents of
all HDLC frames and flag sequence octets via this output data bus, upon the ris-
ing edge of the RxHDLCClk output signal. Hence, the user's System-Side ter-
minal equipment should be designed/configured to sample this data upon the
falling edge of the RxHDLCClk output clock signal.
All other Modes - RxOOF - OOF Defect Indicator Output pin:
The Receive DS3/E3 Framer will assert this output signal whenever it has
declared the Out of Frame (OOF) defect condition with the incoming DS3 or E3
frames. This signal is negated when the Receive DS3/E3 Framer block re-
acquires DS3 or E3 frame synchronization and clears the OOF defect condition.
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