XRT79L71_07 Datasheet, PDF (73/109 Pages) Exar Corporation – 1-CHANNEL DS3/E3 ATM UNI/PPP/CLEAR-CHANNEL FRAMER IC - HARDWARE

XRT79L71
REV. 1.0.0
1-CHANNEL DS3/E3 ATM UNI/PPP/CLEAR-CHANNEL FRAMER IC - HARDWARE
• The Receive Overhead Data Output Interface Block
• The Receive POS-PHY Interface Block
Each of these functional blocks is briefly discussed below. These functional blocks will be discussed in
considerable detail throughout this data sheet.
The Transmit POS-PHY Interface Block
The purpose of the Transmit POS-PHY Interface block is to provide a standard Saturn POS-PHY™ Level 2 or
3 compliant interface to the Link Layer Processor, for writing in the contents of all outbound PPP packets, into
the Transmit FIFO (TxFIFO).
The Transmit POS-PHY Interface block can be configured to operate with either an 8 or 16-bit wide Transmit
POS-PHY Data Bus.
NOTES:
1. The Transmit POS-PHY Interface Block supports POS-PHY Level 3 from a signaling stand-point. The Transmit
POS-PHY Interface block (within the XRT79L71) still only supports a 16-bit wide (not 32-bit wide) POS-PHY Data
Bus and only operates up to 50MHz (not 104MHz).
2. The Transmit POS-PHY Interface block can be configured to support either Out-of-Band Addressing or In-Band
Addressing for Device Selection to WRITE operations. However, since the XRT79L71 is a single-channel device,
we strongly recommend that the user only use Out-of-Band Addressing for Device Selection whenever it is
designed into a Multi-PHY system in which multiple PHY Layer devices are sharing the same POS-PHY Bus.
The Transmit Overhead Data Input Interface Block
The purpose of the Transmit Overhead Data Input Interface block is to permit the user to externally insert his/
her own value for overhead bits into the outbound DS3/E3 data-stream.
The Transmit PPP Packet Processor Block
The purpose of the Transmit PPP Packet Processor block is to read out the contents of the PPP Packets that
have been written into the TxFIFO (via the Transmit POS-PHY Interface block) and perform the following
functions.
• Compute and verify the Transmit POS-PHY Interface Parity value for each byte or (16-bit) word of each
incoming PPP Packet
• To Parse through the contents of each outbound packet for any occurrence of the value 0x7E and 0x7D and
to character-stuff (or replace) these values with strings of values 0x7D5E and 0x7D5D, respectively
• To compute and append either a CRC-16 or CRC-32 value to the back-end of each outbound PPP Packet
• To repeatedly generate and transmit the Flag Sequence Octet, anytime the Transmit PPP Packet Processor
block is NOT processing any PPP Packet data from the TxFIFO (e.g., whenever the TxFIFO is depleted)
• To route this composite stream of PPP packet and Flag Sequence octets to the Transmit DS3/E3 Framer
block for further processing.
The Transmit FEAC Controller Block (DS3, C-bit Parity Applications Only)
The purpose of the Transmit FEAC Controller block is to permit the user to transmit FEAC (Far-End Alarm &
Control) Messages to the remote terminal equipment.
NOTE: The Transmit FEAC Controller block is only active if the XRT79L71 is configured to operate in the DS3, C-bit Parity
Framing format.
The Transmit Trail-Trace Message Controller Block (E3, ITU-T G.832 Applications Only)
The Transmit SSM Controller Block (E3, ITU-T G.832 Applications Only)
The Transmit LAPD Controller Block
The purpose of the Transmit LAPD Controller block is to permit the user to transmit LAPD/PMDL (Path
Maintenance Data Link) Messages to the remote terminal equipment. The Transmit LAPD Controller block
70