XRT79L71_07 Datasheet, PDF (31/109 Pages) Exar Corporation – 1-CHANNEL DS3/E3 ATM UNI/PPP/CLEAR-CHANNEL FRAMER IC - HARDWARE

REV. 1.0.0
PIN #
N3
NAME
TxUClav/
TxPPA
XRT79L71
1-CHANNEL DS3/E3 ATM UNI/PPP/CLEAR-CHANNEL FRAMER IC - HARDWARE
TYPE
DESCRIPTION
O Transmit UTOPIA Interface - Cell Available Output Pin/Transmit POS-PHY
Interface - Packet Data Available Output pin:
The function of this output pin depends upon whether the XRT79L71 has been
configured to operate in the ATM UNI or PPP Mode.
ATM UNI Mode - TxUClav - Transmit UTOPIA Interface - Cell Space Avail-
able Indicator Output pin:
This output pin supports data flow control between the ATM Layer Processor and
the Transmit UTOPIA Interface block. This signal is asserted (e.g., driven
"High") whenever the TxFIFO is capable of receiving at least one more full ATM
cell of data from the ATM Layer processor. This signal is negated (e.g., driven
"Low"), if the TxFIFO is not capable of receiving one more full ATM cell of data
from the ATM Layer processor. The exact behavior of the TxUClav output pin, as
a function of UTOPIA Level is presented below.
Multi-PHY Operation - UTOPIA Level 2:
When the XRT79L71 is operating in a Multi-PHY Application and is configured to
operate in the UTOPIA Level 2 Mode, then this signal will be tri-stated until the
TxUClk cycle following the assertion of a valid address on the Transmit UTOPIA
Address bus input pins (e.g., when the contents on the Transmit UTOPIA
Address bus pins, TxUAddr[4:0], match that which have been assigned to this
particular Transmit UTOPIA Interface block). Afterwards, this output pin will be
driven either "High" or "Low" depending upon the current fill status of the
TxFIFO.
Multi-PHY Operation - UTOPIA Level 3
When the XRT79L71 is operating in a Multi-PHY Application and is configured to
operate in the UTOPIA Level 2 Mode, then this signal will be tri-stated until the
TxUClk cycle following the assertion of a valid address on the Transmit UTOPIA
Address bus input pins (e.g., when the contents on the Transmit UTOPIA
Address bus pins, TxUAddr[4:0], match that which have been assigned to this
particular Transmit UTOPIA Interface block). Afterwards, this output pin will be
driven either "High" or "Low" depending upon the current fill status of the
TxFIFO.
PPP Mode - TxPPA TxPPA - Transmit POS-PHY Interface Packet Space
Available Indicator Output:
The XRT79L71 will drive this output pin "High" whenever a (programmable)
number of bytes of empty space is available (for writing more PPP packet data)
into the TxFIFO. The exact behavior of the TxPPA output pin, as a function of
POS-PHY Level is presented below.
POS-PHY Level 2:
When the XRT79L71 is configured to operate in the POS-PHY Level 2 Mode,
then this signal will be tri-stated until the TxPClk cycle following the assertion of a
valid address on the Transmit POS-PHY Address bus input pins (e.g., if the con-
tents on the Transmit POS-PHY Address bus pins, TxPAddr[4:0], match that
which have been assigned to this particular Transmit POS-PHY Interface block).
Afterwards, this output pin will be driven either "High" or "Low" depending upon
the current fill status of the TxFIFO.
POS-PHY Level 3:
When the XRT79L71 is configured to operate in the POS-PHY Level 3 Mode,
then this signal will be tri-stated until two TxPClk cycles following the assertion of
a valid address on the Transmit POS-PHY Address Bus input pins (e.g., if the
contents on the Transmit POS-PHY Address bus pins, TxPAddr[4:0], match that
which have been assigned to this particular Transmit POS-PHY Interface block).
Afterwards, this output pin will be driven either "High" or "Low" depending upon
the current fill status of the TxFIFO.
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