XRT79L71_07 Datasheet, PDF (35/109 Pages) Exar Corporation – 1-CHANNEL DS3/E3 ATM UNI/PPP/CLEAR-CHANNEL FRAMER IC - HARDWARE

REV. 1.0.0
PIN #
M3
NAME
TxPMod
T3
TxUData_0/
TxPData_0
P4
TxUData_1/
TxPData_1
R4
TxUData_2/
TxPData_2
T4
TxUData_3/
TxPData_3
N5
TxUData_4/
TxPData_4
P5
TxUData_5/
TxPData_5
R5
TxUData_6/
TxPData_6
T5
TxUData_7/
TxPData_7
N6
TxUData_8/
TxPData_8
P6
TxUData_9/
TxPData_9
N4
TxUData_10/
TxPData_10
R6
TxUData_11/
TxPData_11
T6
TxUData_12/
TxPData_12
N7
TxUData_13/
TxPData_13
P7
TxUData_14/
TxPData_14
R7
TxUData_15/
TxPData_15
XRT79L71
1-CHANNEL DS3/E3 ATM UNI/PPP/CLEAR-CHANNEL FRAMER IC - HARDWARE
TYPE
DESCRIPTION
I Transmit PPP Data Bus - Modulo Indicator:
This input pin is used to specify the number of valid packet octets are being
placed on the TxPData[15:0] input pins.
The Link Layer Processor is expected to set this input pin "Low" when both bytes
on the TxPData[15:0] data bus contains valid packet data. Conversely, the Link
Layer Processor is expected to set this input pin "High" when only the upper
octet contains valid packet data.
NOTES:
1. This input pin is only active if the XRT79L71 has been configured to
operate in the PPP Mode and if the Transmit POS-PHY Data Bus has
been configured to be 16-bits wide. In all other case, the user should tie
this input pin to GND.
2. The Link Layer Processor is expected to set this input pin to the
appropriate state, as each 16-bit word is being written into the
TxPData[15:0] data bus.
I Transmit UTOPIA Data Bus Inputs/Transmit POS-PHY Data Bus Inputs:
The function of these input pins depends upon whether the XRT79L71 is operat-
ing in the ATM UNI Mode or in the PPP Mode as described below.
ATM UNI Operation - TxUData[15:0] ] - Transmit UTOPIA Interface Data Bus
Input pins:
These input pins comprise the Transmit UTOPIA Data Bus input pins. Whenever
the ATM Layer Processor wishes to transmit ATM cell data through the
XRT79L71 ATM UNI, it must place this data on these pins. The data, on the
Transmit UTOPIA Data Bus is latched into the Transmit UTOPIA Interface block
upon the rising edge of TxUClk.
NOTES:
1. These input pins are only active (e.g., data will be sampled and latched
into the Transmit UTOPIA Interface block) if the TxUEN input pin is
asserted (e.g., pulled "Low").
2. If the user configures the width of the Transmit UTOPIA Data Bus to be
8-bits, then only the pins TxUData[15:8] are active. In this case, the
user must tie the TxUData[7:0] input pins to GND.
PPP Operation - TxPDATA[15:0] - Transmit POS-PHY Data Bus Input pins:
These input pins comprise the Transmit POS-PHY Data Bus input pins. When a
Link Layer Processor transmits PPP packet data through the XRT79L71, it must
place this data on these pins. The data, on the Transmit POS-PHY Data Bus is
latched into the Transmit POS-PHY Interface block upon the rising edge of TxP-
Clk.
NOTES:
1. These input pins are only active (e.g., data will be sampled and latched
into the Transmit POS-PHY Interface block) if the TxPENB input pin is
asserted (e.g., pulled "Low").
2. If the user configures the width of the Transmit POS-PHY Data Bus to
be 8-bits, then only the pins TxPData[15:8] are active. In this case, the
user must tie the TxPData[7:0] input pins to GND.
3. The user should tie all of these pins to GND to operate the XRT79L71
in either the Clear-Channel Framer or in the High-Speed HDLC
Controller Modes.
32