XRT79L71_07 Datasheet, PDF (48/109 Pages) Exar Corporation – 1-CHANNEL DS3/E3 ATM UNI/PPP/CLEAR-CHANNEL FRAMER IC - HARDWARE

XRT79L71
1-CHANNEL DS3/E3 ATM UNI/PPP/CLEAR-CHANNEL FRAMER IC - HARDWARE
REV. 1.0.0
PIN #
K2
L3
L2
NAME
RxUClkO/
RxPClkO
RxUClk/
RxPClk
RxPERR
TYPE
O
I
O
DESCRIPTION
Receive UTOPIA Interface Clock/Receive POS-PHY Interface Clock Out-
put:
This clock output signal is derived from an internal PLL.
Receive UTOPIA Interface Clock Input/Receive POS-PHY Interface Clock
Input:
The function of this input pin depends upon whether the XRT79L71 is operating
in the ATM UNI or PPP Mode.
ATM UNI Mode - RxUClk:
The byte (or word) data, on the Receive UTOPIA Data bus (RxUData[15:0]) is
updated on the rising edge of this signal. The Receive UTOPIA Interface can
be clocked at rates up to 50 MHz.
PPP Mode - RxPClk:
This byte (or word) data, on the Receive POS-PHY Data Bus (RxPData[15:0]) is
updated on the rising edge of this signal. The Receive POS-PHY Interface can
be clocked at rates up to 50MHz.
NOTE: The user should tie this pin to GND to operate the XRT79L71 in the
Clear-Channel Framer or High-Speed HDLC Controller Modes.
Receive POS-PHY Interface - Error Indicator:
This output pin indicates whether or not the Receive PPP Packet Processor
block has detect any of the following types of erred packets within the incoming
PPP Packet data-stream.
• Packets with FCS Errors·
• Aborted Packets
• RUNT Packets
Anytime the Receive PPP Packet Processor block detects these types of PPP
Packets, then the XRT79L71 will pulse this output pin "High" coincident to
whenever the Receive POS-PHY Interface block outputs the very last byte or
16-bit word of the erred packet via the RxPData[15:0] output pins.The
XRT79L71 will hold this output pin "Low" at all other times.
NOTE: This output pin is only valid if the XRT79L71 has been configured to
operate in the PPP Mode.
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