XRT79L71_07 Datasheet, PDF (23/109 Pages) Exar Corporation – 1-CHANNEL DS3/E3 ATM UNI/PPP/CLEAR-CHANNEL FRAMER IC - HARDWARE

REV. 1.0.0
PIN #
C2
NAME
TxGFCClk
B8
TxNib_3/
TxPOHIns/
TxHDLCDat_3
XRT79L71
1-CHANNEL DS3/E3 ATM UNI/PPP/CLEAR-CHANNEL FRAMER IC - HARDWARE
TYPE
DESCRIPTION
O Transmit GFC Nibble-Field Serial Input port - Clock Output signal:
This signal, along with TxGFC and TxGFCMSB combine to function as the
Transmit GFC Nibble-field serial input port. This output signal functions as the
demand clock signal for this port. The user will specify the value of the GFC
field, within a given ATM cell, by serially transmitting its four bit-value into the
TxGFC input pin. The Transmit GFC Nibble-Field serial input port will latch the
contents of TxGFC upon the rising edge of this clock signal. Hence, the System-
Side terminal equipment should be designed to place its outbound GFC bits on
to the TxGFC line, upon the falling edge of this clock signal.
NOTE: This output pin is only active if the XRT79L71 has been configure to
operate in the ATM UNI Mode.
I Transmit Nibble Interface - Bit 3/Transmit PLCP Path Overhead Insert
enable/Transmit HDLC Controller Data Bus - Bit 3 input:
The function of this input pin depends upon whether the XRT79L71 is configured
to operate in the Clear-Channel Framer Mode, the High-Speed HDLC Controller
Mode or in the ATM/PLCP Mode.
Clear-Channel Framer Mode - TxNib_3 - Transmit Nibble Interface - Bit 3:
If the XRT79L71 is configured to operate in the Nibble-Parallel Mode, then this
input pin will function as the bit 3 (MSB) input to the Transmit Nibble-Parallel
input interface. The Transmit Payload Data Input Interface block will sample this
signal (along with TxNib_0 through TxNib_2) upon the falling edge of TxNibClk.
NOTE: This input pin is inactive if the XRT79L71 is configured to operate in the
Serial Mode.
ATM/PLCP Mode - TxPOHInsTxPOHIns - Transmit PLCP Path Overhead
Insert Enable Input pin:
f the XRT79L71 is configured to operate in the ATM Mode, and if (within the ATM
Mode, the chip is also configured to operate in the PLCP Mode), then this input
pin functions as the Transmit PLCP Path Overhead Port - Enable input pin. In
this mode, the user can externally insert desired path overhead byte values into
the outbound PLCP frames.
The Transmit PLCP Path Overhead Input port becomes active whenever the
user asserts this input pin by pulling it "High". Once this occurs, the data, resid-
ing upon the TxPOH input pin will be sampled upon the rising edge of the TxPO-
HClk signal.
NOTE: This input pin is inactive (and should be tied to GND) if the XRT79L71 is
configured to operate in the Direct-Mapped ATM Mode.
High-Speed HDLC Controller Mode - TxHDLCDat_3 - Transmit High-Speed
HDLC Controller Data Bus - Bit 3 Input pin:
If the XRT79L71 is configured to operate in the High-Speed HDLC Controller
mode, then this input pin will function as Bit 3 within the Transmit High-Speed
HDLC Controller Input Interface block - Input Data Bus (e.g., the TxHDL-
CData[7:0] input pins).
The Transmit High-Speed HDLC Controller Input Interface block provides the
System-Side terminal equipment with a byte-wide Transmit High-Speed HDLC
Controller clock output signal (TxHDLCClk). The Transmit High-Speed HDLC
Controller Input Interface sample the data residing on this input pin (along with
the rest of the TxHDLCData[7:0] input pins) upon the rising edge of the TxHDL-
CClk clock output signal.
NOTE: This input pin is inactive (and should be tied to GND) if the XRT79L71
has been configured to operate in the PPP Mode.
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