XRT79L71_07 Datasheet, PDF (75/109 Pages) Exar Corporation – 1-CHANNEL DS3/E3 ATM UNI/PPP/CLEAR-CHANNEL FRAMER IC - HARDWARE

XRT79L71
REV. 1.0.0
1-CHANNEL DS3/E3 ATM UNI/PPP/CLEAR-CHANNEL FRAMER IC - HARDWARE
The purpose of the Receive DS3/E3 Framer block is to acquire and maintain Frame Synchronization with the
incoming DS3/E3 data-stream that it receives from the Receive DS3/E3 LIU Block. As the Receive DS3/E3
Framer block performs this task, it will also do the following.
• It will declare and clear the LOS defect condition
• It will declare and clear the LOF/OOF defect condition
• It will declare and clear the AIS defect condition
• It will declare and clear the FERF/RDI defect condition
• It will detect and flag the occurrence of P-bit, CP-bit and Framing bit errors (DS3 Applications)
• It will detect and flag the occurrence of BIP-8 Errors (E3, ITU-T G.832 Applications)
• It will detect and flag the occurrence of BIP-4 Errors (E3, ITU-T G.751 Applications)
• It will detect and flag the occurrences of FEBE/REI Events
• It will detect and flag any occurrences of LCVs (Line Code Violations) and EXZs (Excessive Zero) events
within the incoming DS3/E3 line signal
• It will extract the payload bits (out from each incoming DS3 or E3 frame) and it will route this data to the
Receive PPP Packet Processor block for further processing.
The Receive LAPD Controller Block
The purpose of the Receive LAPD Controller block is to permit the user to receive LAPD/PMDL (Path
Maintenance Data Link) Messages from the remote terminal equipment. The Receive LAPD Controller block
comes with a Receive LAPD Controller (not to be confused with the Receive High-Speed HDLC Controller
block) and 90 bytes of on-chip RAM (for storage of inbound PMDL Messages) after reception.
The Receive SSM Controller Block (E3, ITU-T G.832 Applications Only)
The Receive Trail-Trace Message Controller Block (E3, ITU-T G.832 Applications Only)
The Receive FEAC Controller Block (DS3, C-bit Parity Applications Only)
The purpose of the Receive FEAC Controller block is to permit the user to receive FEAC (Far-End Alarm &
Control) Messages from the remote terminal equipment.
NOTE: The Receive FEAC Controller block is only active if the XRT79L71 is configured to operate in the DS3, C-bit Parity
Framing format.
The Receive PPP Packet Processor Block
The purpose of the Receive PPP Packet Processor block is to extract out the payload data (being carried by
the incoming DS3/E3 data-stream) and to perform the following operations on it.
• Identification/Location of boundaries of incoming PPP packets
• Computation and Verification of either the CRC-16 or CRC-32 values within the incoming PPP Packets
• To Parse through the contents of each inbound packet for any occurrences of the values 0x7D5E and
0x7D5D and to character de-stuff (or replace) these values with strings of 0x7E and 0x7D, respectively
• To terminate any incoming Flag Sequence octets
• To flag the occurrence of any incoming RUNT packets
• To flag the occurrence of any incoming Aborted Packets
The Receive Overhead Data Output Interface Block
The purpose of the Receive Overhead Data Output Interface block is to permit the user to extract out the
overhead bits (within the incoming DS3/E3 data-stream) and to route this data to some off-chip System-Side
Terminal Equipment circuitry.
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