XRT79L71_07 Datasheet, PDF (56/109 Pages) Exar Corporation – 1-CHANNEL DS3/E3 ATM UNI/PPP/CLEAR-CHANNEL FRAMER IC - HARDWARE

XRT79L71
1-CHANNEL DS3/E3 ATM UNI/PPP/CLEAR-CHANNEL FRAMER IC - HARDWARE
REV. 1.0.0
PIN #
R13
K16
NAME
RRING
CLKOUT
TYPE
I
O
DESCRIPTION
Receive Input - Negative Polarity Signal:
This input pin, along with the RTIP input pin, functions as the Receive DS3/E3
Line Signal input for the XRT79L71.
The user is expected to connect this signal and the RTIP input signal to a 1:1
transformer.
Whenever the RTIP/RRING input pins are receiving a positive-polarity pulse
within the incoming DS3 or E3 line signal, then this input pin will be pulsed to a
lower-voltage than that of the RTIP input pin.
Conversely, whenever the RTIP/RRING input pins are receiving a negative-
polarity pulse within the incoming DS3 or E3 line signal, then this input pin will be
pulsed to a higher-voltage than that of the RTIP input pin.
SFM Synthesizer/Clock Recovery PLL Reference Clock Output:
The exact source of this output signal depends upon whether or not the
XRT79L71 has been configured to operate in the SFM (Single-Frequency Mode)
Mode, as described below.
If the XRT79L71 is configured to operate in the SFM Mode
If the XRT79L71 has been configured to operate in the SFM Mode, then the
CLKOUT output pin (if enabled) will output a 44.736MHz clock signal (if the
XRT79L71 is configured to operate in the DS3 Mode) or a 34.368MHz clock sig-
nal (if the XRT79L71 is configured to operate in the E3 Mode.
NOTES:
1. In this case, the 44.736MHz or 33.368MHz clock (that is output via the
CLKOUT signal) will ultimately be derived from the 12.288MHz clock
signal that is being applied to the DS3CLK/SFMCLK input pin.2.
2. This output pin is only active if Bit 6 (SFM Clock Out Enable), within the
LIU Channel Control Register (Address = 0x1306) has been set to "1".
If the XRT79L71 is NOT configured to operate in the SFM Mode
If the XRT79L71 has NOT been configured to operate in the SFM Mode, then fre-
quencies of the CLKOUT output signal will be as follows.
a. If the XRT79L71 has been configured to operate in the DS3 Mode, then
the XRT79L71 will simply output a buffered version of the signal that is
being applied to the DS3CLK/SFMCLK input pin (which should be a
44.736MHz clock signal).
b. If the XRT79L71 has been configured to operate in the E3 Mode, then the
XRT79L71 will simply output a buffered version of the signal that is being
applied to the E3CLK input pin (which should be a 34.368MHz clock
signal).
NOTE: This output pin is only if Bit 6 (SFM Clock Out Enable), within the LIU
Channel Control Register (Address = 0x1306) has been set to "1".
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