XRT79L71_07 Datasheet, PDF (25/109 Pages) Exar Corporation – 1-CHANNEL DS3/E3 ATM UNI/PPP/CLEAR-CHANNEL FRAMER IC - HARDWARE

REV. 1.0.0
PIN #
D8
NAME
TxNib_1/
Tx8KREF/
TxHDLCDat_1
XRT79L71
1-CHANNEL DS3/E3 ATM UNI/PPP/CLEAR-CHANNEL FRAMER IC - HARDWARE
TYPE
DESCRIPTION
I Transmit Nibble Input Interface - Bit 1/Transmit PLCP Framing 8kHz Refer-
ence Input/Transmit HDLC Controller Data Bus - Bit 1 Input:
The function of this input pin depends upon whether the XRT79L71 is configured
to operate in the Clear-Channel Framer Mode, the High-Speed HDLC Controller
Mode, or in the ATM/PLCP Mode.
Clear-Channel Framer Mode - TxNib_1 - Transmit Nibble Interface -Bit 1:
If the XRT79L71 is configured to operate in the Nibble-Parallel Mode, then this
input pin will function as the bit 1 input to the Transmit Nibble-Parallel input inter-
face. The Transmit Payload Data Input Interface block will sample this signal
(along with TxNib_0, TxNib_2 and TxNib_3) upon the falling edge of TxNibClk.
NOTE: This input pin is inactive (and should be tied to GND) if the XRT79L71 is
configured to operate in the Serial Mode.
ATM/PLCP Mode - Tx8KREF - Transmit PLCP Framing 8kHz Reference
Input pin:
If the XRT79L71 is configured to operate in the ATM/PLCP Mode, then the
Transmit PLCP Processor can be configured to synchronize its PLCP frame gen-
eration to this input clock signal. The Transmit PLCP Processor will also use
this input signal to compute the nibble-trailer stuff opportunities.
NOTE: This input pin is inactive (and should be tied to GND) if the use has
configured the XRT79L71 to operate in the Direct-Mapped ATM Mode.
High-Speed HDLC Controller Mode - TxHDLCDat_1 - Transmit HDLC Con-
troller Data Bus - Bit 1 Input pin:
If the XRT79L71 is configured to operate in the High-Speed HDLC Controller
mode, then this input pin will function as Bit 1 within the Transmit High-Speed
HDLC Controller Input Interface block - Input Data Bus (e.g., the TxHDL-
CData[7:0] input pins).
The Transmit High-Speed HDLC Controller Input Interface block provides the
System-Side terminal equipment with a byte-wide Transmit HDLC Controller
clock output signal (TxHDLCClk). The Transmit High-Speed HDLC Controller
Input Interface block samples the data residing on this input pin (along with the
rest of the TxHDLCData[7:0] input pins) upon the rising edge of the TxHDLCClk
clock output signal.
NOTE: This input pin is inactive and should be tied to GND, if the XRT79L71 has
been configured to operate in either the PPP or in the Direct-Mapped
ATM Mode.
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