XRT79L71_07 Datasheet, PDF (16/109 Pages) Exar Corporation – 1-CHANNEL DS3/E3 ATM UNI/PPP/CLEAR-CHANNEL FRAMER IC - HARDWARE

XRT79L71
1-CHANNEL DS3/E3 ATM UNI/PPP/CLEAR-CHANNEL FRAMER IC - HARDWARE
REV. 1.0.0
PIN #
L16
B10
A11
NAME
NibbleIntf
TxFrame
TxFrameRef
TYPE
DESCRIPTION
I Nibble Interface Select Input pin:
This input pin is used to configure the Transmit Payload Data Input Interface and
the Receive Payload Data Output Interface blocks to operate in either the Serial
or the Nibble-Parallel Mode.
Setting this input pin "High" configures each of these blocks to operate in
the Nibble-Parallel Mode.
In this mode, the Transmit Payload Data Input Interface block will accept the out-
bound payload data from the System-Side terminal equipment in a nibble-paral-
lel manner via the TxNib[3:0] input pins. Further, the Receive Payload Data
Output Interface block will output inbound payload data to the System-Side ter-
minal equipment in a nibble-parallel via the RxNib[3:0] output pins.
Setting this input pin "Low" configures each of these blocks to operate in
the Serial Mode.
In this mode, the Transmit Payload Data Input Interface block will accept the out-
bound payload data from the System-Side terminal equipment in a serial manner
via the TxSer input pin. Further, the Receive Payload Data Output Interface
block will output the inbound payload data to the System-Side terminal equip-
ment in a serial manner, via the RxSer output pin.
NOTE:
This input pin is only active if the XRT79L71 has been configured to
operate in the Clear-Channel Framer Mode. The user is advised to tie
this input pin to GND if the user intends to configure the XRT79L71 to
operate in the ATM UNI or PPP Modes.
O Transmit End of DS3/E3 Frame Indicator:
This output pin is pulse "High" for one DS3 or E3 clock period, when the Transmit
Section of the XRT79L71 is processing the last bit of a given DS3 or E3 frame.
The implications of this output pin, for each mode of operation, are described
below.
ATM UNI/PPP/High-Speed HDLC Controller Mode:
This output pin serves as an end-of-frame indication to the System-Side terminal
equipment.
Clear-Channel Framer Mode:
If the XRT79L71 is configured to operate in the Clear-Channel Framer mode,
then this output pin serves to alert the System-Side Terminal Equipment that it
needs to begin transmission of a new DS3 or E3 frame. Hence, the System-Side
Terminal Equipment uses this output signal to maintain Framing Alignment with
the XRT79L71.
I Transmit DS3/E3 Framer - Framing Alignment Input pin:
If the the Transmit Section of the XRT79L71 is configured to operate in the
Local-Timing/Frame-Slave Mode, then the Transmit DS3/E3 Framer block will
use this input signal as the Framing Reference.
When the XRT79L71 is configured to operate in this mode any rising edge at this
input pin will cause the Transmit DS3/E3 Framer block to begin its creation of a
new DS3 or E3 frame. Consequently, the user must supply a clock signal that is
equivalent to the DS3 or E3 frame rates to this input pin. Further, it is imperative
that this clock signal be synchronized with the 44.736MHz or 34.368MHz clock
signal applied to the TxInClk input pin.
NOTE: This input pin should be tied to GND if it is not to be used as the Transmit
DS3/E3 Framer block - Framing Reference input signal.
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