XRT79L71_07 Datasheet, PDF (62/109 Pages) Exar Corporation – 1-CHANNEL DS3/E3 ATM UNI/PPP/CLEAR-CHANNEL FRAMER IC - HARDWARE

XRT79L71
1-CHANNEL DS3/E3 ATM UNI/PPP/CLEAR-CHANNEL FRAMER IC - HARDWARE
REV. 1.0.0
• To generate and transmit DS3 pulses that complies with the Isolated Pulse Template requirements per
Bellcore GR-499-CORE
• To generate and transmit E3 pulses that complies with the ITU-T G.703 Pulse Template requirements for E3
applications.
The Receive DS3/E3 LIU Block
The purpose of the Receive DS3/E3 LIU Block is to receive a DS3/E3 line signal from the remote terminal
equipment, and to perform the following operations
• To decode this incoming signal from the B3ZS Line Code (for DS3 Applications) or the HDB3 Line Code (for
E3 Applications) into a binary data-stream
• To route this binary data-stream to the Receive DS3/E3 Framer block for further processing
• To detect and flag the occurrence of LCVs (Line Code Violations) and EXZs (Excessive Zeros)
• To insure that the XRT79L71 meets all of the following Receive requirements.
a. The Receive Sensitivity requirements for DS3 Applications (e.g., able to receive a DSX-3 type of signal
through at least 450 feet of cable loss)
b. The Receive Sensitivity requirements for E3 Applications (e.g., able to receive an E3 signal over 12dB of
cable loss)
c. To comply with the Category I and II Jitter Tolerance Requirements per Bellcore GR-499-CORE (for DS3
Applications)
d. To comply with the Jitter Tolerance Requirements per ITU-T G.832 (for E3 Applications)
e. To comply with the Interference Margin Requirements of 20dB, per ITU-T G.703 (for E3 Applications)
The Receive DS3/E3 Framer Block
The purpose of the Receive DS3/E3 Framer block is to acquire and maintain Frame Synchronization with the
incoming DS3/E3 data-stream that is receives from the Receive DS3/E3 LIU Block. As the Receive DS3/E3
Framer block performs this task, it will also do the following.
• It will declare and clear the LOS defect condition
• It will declare and clear the LOF/OOF defect condition
• It will declare and clear the AIS defect condition
• It will declare and clear the FERF/RDI defect condition
• It will detect and flag the occurrences of P-bit, CP-bit and Framing bit errors (DS3 Applications)
• It will detect and flag the occurrence of BIP-8 Errors (E3, ITU-T G.832 Applications)
• It will detect and flag the occurrence of BIP-4 Errors (E3, ITU-T G.751 Applications)
• It will detect and flag the occurrence of FEBE/REI Events
• It will route all PMDL data to the Receive LAPD Controller block for further processing
• It will route all Overhead bits/bytes to the Receive Overhead Data Output Interface block for further
processing
• It will route all DS3/E3 data to the Receive Payload Data Output Interface block.
The Receive SSM Controller Block (E3, ITU-T G.832 Applications Only)
The Receive Trail-Trace Message Controller Block (E3, ITU-T G.832 Applications Only)
The Receive FEAC Controller Block (DS3 Applications Only)
The purpose of the Receive FEAC Controller block is to permit the user to receive FEAC (Far-End Alarm &
Control) Messages from the remote terminal equipment.
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