XRT79L71_07 Datasheet, PDF (21/109 Pages) Exar Corporation – 1-CHANNEL DS3/E3 ATM UNI/PPP/CLEAR-CHANNEL FRAMER IC - HARDWARE

REV. 1.0.0
PIN #
B3
NAME
TxPOHClk
B9
TxOHInd/
TxPFrame/
TxHDLCDat_6/
XRT79L71
1-CHANNEL DS3/E3 ATM UNI/PPP/CLEAR-CHANNEL FRAMER IC - HARDWARE
TYPE
DESCRIPTION
O Transmit PLCP Frame POH Byte Insertion Clock:
This pin, along with the TxPOH and the TxPOHMSB input pins, function as the
Transmit PLCP Frame POH Byte serial input port. This output pin functions as a
clock output signal that is be used to sample the user's POH data at the TxPOH
input pin. This output pin is always active, independent of the state of the TxPO-
HIns pin.
NOTE: This output pin is only active if the XRT79L71 has been configured to
operate in the ATM/PLCP Mode.
I/O Transmit Overhead Data Indicator Output/Transmit PLCP Frame Boundary
Indicator Output/Transmit HDLC Controller Data Bit 6 input pin:
The function of these input/output pins depends upon whether the XRT79L71
has been configured to operate in the Clear-Channel Framer Mode, the ATM/
PLCP Mode or the High-Speed HDLC Mode.
Clear-Channel Framer Mode - TxOHInd - Transmit Overhead Data Indicator
Output pin:
In the Clear-Channel Framer Mode, this output pin can be configured to function
as the transmit overhead data indicator for the System-Side terminal equipment,
or as a Gapped-Clock output for the Transmit Payload Data Input Interface. This
output pin is pulsed "High" for one DS3 or E3 bit period in order to indicate to the
System-Side terminal equipment that the Transmit Section of the Framer is going
to be processing an overhead bit, upon the next rising edge of TxInClk., and will
NOT latch the data that is applied to the TxSer input pin. Therefore, when the
System-Side terminal equipment samples the TxOHInd output pin "High", then it
must not apply the next payload bit to TxSer input pin. This output pin serves as
a warning that this particular payload bit is going to be ignored by the Transmit
Section of the Framer, and will not be inserted into payload bits, within the out-
bound DS3 or E3 data stream.
ATM/PLCP Mode - TxPFrame:
If the XRT79L71 is configured to operate in the ATM UNI/PLCP Mode, then this
output pin will denote the boundaries of outbound PLCP frames, as they are
being processed by the Transmit PLCP Processor block. This output pulses
"High" when the last nibble of a given PLCP frame is being routed to the Trans-
mit DS3/E3 Framer block.
This output pin is inactive if the XRT79L71 is operating in the Direct-Mapped
ATM Mode.
High-Speed HDLC Controller Mode - TxHDLCDat_6 - Transmit High-Speed
HDLC Controller Bit 6 Input pin:
If the XRT79L71 is configured to operate in the High-Speed HDLC Controller
mode, then this input pin will function as Bit 6 within the Transmit High-Speed
HDLC Controller Input Interface block - Input Data Bus (e.g., the TxHDL-
CData[7:0] input pins).
The Transmit High-Speed HDLC Controller Input Interface block provides the
System-Side terminal equipment with a byte-wide Transmit High-Speed HDLC
Controller clock output signal (TxHDLCClk). The Transmit High-Speed HDLC
Controller Input Interface block sample the data residing on this input pin (along
with the rest of the TxHDLCData[7:0] input pins) upon the rising edge of the TxH-
DLCClk clock output signal.
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