XRT79L71_07 Datasheet, PDF (12/109 Pages) Exar Corporation – 1-CHANNEL DS3/E3 ATM UNI/PPP/CLEAR-CHANNEL FRAMER IC - HARDWARE

XRT79L71
1-CHANNEL DS3/E3 ATM UNI/PPP/CLEAR-CHANNEL FRAMER IC - HARDWARE
PIN DESCRIPTIONS
REV. 1.0.0
PIN #
H16
NAME
µPCLK
TYPE
DESCRIPTION
I Microprocessor Interface Clock Input:
This clock input signal is only used if the Microprocessor Interface has been config-
ured to operate in one of the Synchronous Modes (e.g., Power PC 403 Mode). If the
Microprocessor Interface is configured to operate in one of these modes, then it uses
this clock signal to do the following.
• To sample the CS, WR/R/W, A[14:0], D[7:0], RD/DS and DBEN input pins, and
• To update the state of the D[7:0] and the RDY/DTACK output signals.
NOTES:
1. The Microprocessor Interface can work with µPCLK frequencies ranging up
to 33MHz.
2. This pin is inactive if the user has configured the Microprocessor Interface
to operate in either the Intel-Asynchronous or the Motorola-Asynchronous
Modes. In this case, the user should tie this pin to GND.
B16
WR/R/W
I Write Strobe/Read-Write Operation Identifier:
The exact function of this input pin depends upon which mode the Microprocessor
Interface has been configured to operate in.
Intel-Asynchronous Mode - WR - Write Strobe Input:
If the Microprocessor Interface is configured to operate in the Intel-Asynchronous
Mode, then this input pin functions as the WR (Active "Low" WRITE Strobe) input sig-
nal from the Microprocessor. Once this active-"Low" signal is asserted, then the
input buffers (associated with the Bi-Directional Data Bus pin, D[7:0]) will be enabled.
The Microprocessor Interface will latch the contents on the Bi-Directional Data Bus
(into the target register or address location, within the XRT79L71) upon the rising
edge of this input pin.
Motorola-Asynchronous Mode - R/W - Read/Write Operation Identification
Input Pin:
If the Microprocessor Interface is operating in the Motorola-Asynchronous Mode,
then this pin is functionally equivalent to the R/W input pin. In the Motorola Mode, a
READ operation occurs if this pin is held at a logic "1", coincident to a falling edge of
the RD/DS (Data Strobe) input pin. Similarly a WRITE operation occurs if this pin is
at a logic "0", coincident to a falling edge of the RD/DS (Data Strobe) input pin.
Power PC 403 Mode - R/W - Read/Write Operation Identification Input:
If the Microprocessor Interface is configured to operate in the Power PC 403 Mode,
then this input pin will function as the Read/Write Operation Identification Input pin.
Anytime the Microprocessor Interface samples this input signal at a logic "Low"
(while also sampling the CS input pin "Low") upon the rising edge of mPCLK, then
the Microprocessor Interface will (upon the very same rising edge of mPCLK) latch
the contents of the Address Bus (A[14:0]) into the Microprocessor Interface circuitry,
in preparation for this forthcoming READ operation. At some point (later in this
READ operation) the Microprocessor will also assert the DBEN/OE input pin, and the
Microprocessor Interface will then place the contents of the target register (or
address location within the XRT79L71) upon the Bi-Directional Data Bus pins
(D[7:0]), where it can be read by the Microprocessor.
Anytime the Microprocessor Interface samples this input signal at a logic "High"
(while also sampling the CS input pin a logic "Low") upon the rising edge of µPCLK,
then the Microprocessor Interface will (upon the very same rising edge of µPCLK)
latch the contents of the Address Bus (A[14:0]) into the Microprocessor Interface cir-
cuitry, in preparation for the forthcoming WRITE operation. At some point (later in
this WRITE operation) the Microprocessor will also assert the RD/DS/WE input pin,
and the Microprocessor Interface will then latch the contents of the Bi-Directional
Data Bus (D[7:0]) into the contents of the target register or buffer location within the
XRT79L71.
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