XRT79L71_07 Datasheet, PDF (43/109 Pages) Exar Corporation – 1-CHANNEL DS3/E3 ATM UNI/PPP/CLEAR-CHANNEL FRAMER IC - HARDWARE

REV. 1.0.0
PIN #
A5
NAME
RxPOH/
RxSer
XRT79L71
1-CHANNEL DS3/E3 ATM UNI/PPP/CLEAR-CHANNEL FRAMER IC - HARDWARE
TYPE
O
DESCRIPTION
Receive PLCP Path Overhead Output pin/Receive Serial Output pin:
The function of this output depends upon whether the XRT79L71 has been con-
figured to operate in the ATM/PLCP Mode or in the Clear-Channel Framer
Mode.
ATM/PLCP Mode - RxPOH (Receive PLCP Path Overhead Output pin):
This output pin along with the RxPOHClk, RxPOHFrame and RxPOHIns pins
comprise the Receive PLCP Frame POH Byte serial output port. For each
PLCP frame, that is received by the Receive PLCP Processor, this serial output
port will output the contents of all 12 POH (Path Overhead) bytes. The data that
is output via this pin, is updated on the rising edge of the RxPOHClk output
clock signal. The RxPOHFrame pin will pulse "High" whenever the first bit of
the Z6 byte is being output via this output pin.
NOTE: This pin is not active if the user has configured the XRT79L71 to operate
in the ATM UNI/Direct Mapped Mode
Clear-Channel Framer Mode - RxSer RxSer (Receive Serial Output pin):
If the XRT79L71 is configured to operate in the Clear-Channel Framer/Serial
Mode, then the chip will output all received data, via this output pin. This output
signal will be updated upon the rising edge of RxClk.
NOTE: The user should either configure the the Receive Payload Data Output
Interface block to operate in the Gapped-Clock Mode, or the user must
validate the sampling of each bit from the RxSer output with the state of
RxOHInd' output pin, in order to prevent the System-Side terminal
equipment from sampling overhead bits.
This output pin is only active if the XRT79L71 has been configured to operate in
the ATM/PLCP or the Clear-Channel Framer/Serial Mode. This pin is inactive
for all remaining modes of operation.
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