EZ-USB Datasheet, PDF (67/334 Pages) Cypress Semiconductor – The EZ-USB USB Integrated Circuit

4.4 I²C Controller
The USB core contains an I ²C controller for boot loading and general-purpose I²C bus
interface. This controller uses the SCL (Serial Clock) and SDA (Serial Data) pins. I2C
Controller describes how the boot load operates at power-on to read the contents of an
external serial EEPROM to determine the initial EZ-USB FX configuration. The boot
loader operates automatically, while the 8051 is held in reset. The last section of this chap-
ter describes the operating details of the boot loader.
After the boot sequence completes and the 8051 is brought out of reset, the general-pur-
pose I ²C controller is available to the 8051 for interface to external I²C devices, such as
other EEPROMS, I/O chips, audio/video control chips, etc.
4.5 8051 I²C Controller
start
SDA
D7
D6
D5
D4
D3
D2
D1
D0
ACK
SCL
1
2
3
4
5
6
7
8
9
stop
Figure 4-5. General I²C Transfer
Figure 4-5 illustrates the waveforms for an I²C transfer. SCL and SDA are open-drain EZ-
USB pins, which must be pulled up to Vcc with external resistors. The EZ-USB chip is an
I ²C bus master only, meaning that it synchronizes data transfers by generating clock
pulses on SCL by driving low. Once the master drives SCL low, external slave devices can
also drive SCL low to extend clock cycle times.
To synchronize I²C data, serial data (SDA) is permitted to change state only while SCL is
low, and must be valid while SCL is high. Two exceptions to this rule are used to generate
START and STOP conditions. A START condition is defined as SDA going low, while
SCL is high, and a STOP condition is defined as SDA going high, while SCL is high. Data
is sent MSB first. During the last bit time (clock #9 in Figure 4-5), the master (EZ-USB)
floats the SDA line to allow the slave to acknowledge the transfer by pulling SDA low.
Page 4-6
Chapter 4. EZ-USB CPU
EZ-USB TRM v1.9